Lines Matching +full:0 +full:xee000000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
121 a57_0: cpu@0 {
123 reg = <0x0>;
137 reg = <0x1>;
150 reg = <0x100>;
164 reg = <0x101>;
176 reg = <0x102>;
188 reg = <0x103>;
198 L2_CA57: cache-controller-0 {
215 #clock-cells = <0>;
217 clock-frequency = <0>;
223 #clock-cells = <0>;
225 clock-frequency = <0>;
232 #clock-cells = <0>;
233 clock-frequency = <0>;
260 #clock-cells = <0>;
261 clock-frequency = <0>;
276 reg = <0 0xe6020000 0 0x0c>;
287 reg = <0 0xe6050000 0 0x50>;
291 gpio-ranges = <&pfc 0 0 16>;
302 reg = <0 0xe6051000 0 0x50>;
306 gpio-ranges = <&pfc 0 32 29>;
317 reg = <0 0xe6052000 0 0x50>;
321 gpio-ranges = <&pfc 0 64 15>;
332 reg = <0 0xe6053000 0 0x50>;
336 gpio-ranges = <&pfc 0 96 16>;
347 reg = <0 0xe6054000 0 0x50>;
351 gpio-ranges = <&pfc 0 128 18>;
362 reg = <0 0xe6055000 0 0x50>;
366 gpio-ranges = <&pfc 0 160 26>;
377 reg = <0 0xe6055400 0 0x50>;
381 gpio-ranges = <&pfc 0 192 32>;
392 reg = <0 0xe6055800 0 0x50>;
396 gpio-ranges = <&pfc 0 224 4>;
406 reg = <0 0xe6060000 0 0x50c>;
413 reg = <0 0xe60f0000 0 0x1004>;
426 reg = <0 0xe6130000 0 0x1004>;
445 reg = <0 0xe6140000 0 0x1004>;
464 reg = <0 0xe6148000 0 0x1004>;
482 reg = <0 0xe6150000 0 0x0bb0>;
486 #power-domain-cells = <0>;
493 reg = <0 0xe6160000 0 0x018c>;
499 reg = <0 0xe6180000 0 0x0400>;
505 reg = <0 0xe6198000 0 0x100>,
506 <0 0xe61a0000 0 0x100>,
507 <0 0xe61a8000 0 0x100>;
521 reg = <0 0xe61c0000 0 0x200>;
522 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
535 reg = <0 0xe61e0000 0 0x30>;
549 reg = <0 0xe6fc0000 0 0x30>;
564 reg = <0 0xe6fd0000 0 0x30>;
579 reg = <0 0xe6fe0000 0 0x30>;
593 reg = <0 0xffc00000 0 0x30>;
607 #size-cells = <0>;
610 reg = <0 0xe6500000 0 0x40>;
615 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
616 <&dmac2 0x91>, <&dmac2 0x90>;
624 #size-cells = <0>;
627 reg = <0 0xe6508000 0 0x40>;
632 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
633 <&dmac2 0x93>, <&dmac2 0x92>;
641 #size-cells = <0>;
644 reg = <0 0xe6510000 0 0x40>;
649 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
650 <&dmac2 0x95>, <&dmac2 0x94>;
658 #size-cells = <0>;
661 reg = <0 0xe66d0000 0 0x40>;
666 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
674 #size-cells = <0>;
677 reg = <0 0xe66d8000 0 0x40>;
682 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
690 #size-cells = <0>;
693 reg = <0 0xe66e0000 0 0x40>;
698 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
706 #size-cells = <0>;
709 reg = <0 0xe66e8000 0 0x40>;
714 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
722 #size-cells = <0>;
726 reg = <0 0xe60b0000 0 0x425>;
731 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
740 reg = <0 0xe6540000 0 0x60>;
746 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
747 <&dmac2 0x31>, <&dmac2 0x30>;
758 reg = <0 0xe6550000 0 0x60>;
764 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
765 <&dmac2 0x33>, <&dmac2 0x32>;
776 reg = <0 0xe6560000 0 0x60>;
782 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
783 <&dmac2 0x35>, <&dmac2 0x34>;
794 reg = <0 0xe66a0000 0 0x60>;
800 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
811 reg = <0 0xe66b0000 0 0x60>;
817 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
827 reg = <0 0xe6590000 0 0x200>;
830 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
831 <&usb_dmac1 0>, <&usb_dmac1 1>;
844 reg = <0 0xe6590630 0 0x02>;
849 #clock-cells = <0>;
859 reg = <0 0xe65a0000 0 0x100>;
873 reg = <0 0xe65b0000 0 0x100>;
887 reg = <0 0xe65ee000 0 0x90>;
893 #phy-cells = <0>;
900 reg = <0 0xe6700000 0 0x10000>;
929 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
942 reg = <0 0xe7300000 0 0x10000>;
971 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
984 reg = <0 0xe7310000 0 0x10000>;
1025 reg = <0 0xe6740000 0 0x1000>;
1026 renesas,ipmmu-main = <&ipmmu_mm 0>;
1033 reg = <0 0xe7740000 0 0x1000>;
1041 reg = <0 0xe6570000 0 0x1000>;
1049 reg = <0 0xe67b0000 0 0x1000>;
1058 reg = <0 0xec670000 0 0x1000>;
1066 reg = <0 0xfd800000 0 0x1000>;
1074 reg = <0 0xfd950000 0 0x1000>;
1082 reg = <0 0xfe6b0000 0 0x1000>;
1090 reg = <0 0xfebd0000 0 0x1000>;
1099 reg = <0 0xe6800000 0 0x800>;
1137 rx-internal-delay-ps = <0>;
1138 tx-internal-delay-ps = <0>;
1141 #size-cells = <0>;
1148 reg = <0 0xe6c30000 0 0x1000>;
1164 reg = <0 0xe6c38000 0 0x1000>;
1180 reg = <0 0xe66c0000 0 0x8000>;
1205 reg = <0 0xe6e30000 0 0x8>;
1215 reg = <0 0xe6e31000 0 0x8>;
1225 reg = <0 0xe6e32000 0 0x8>;
1235 reg = <0 0xe6e33000 0 0x8>;
1245 reg = <0 0xe6e34000 0 0x8>;
1255 reg = <0 0xe6e35000 0 0x8>;
1265 reg = <0 0xe6e36000 0 0x8>;
1276 reg = <0 0xe6e60000 0 0x40>;
1282 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1283 <&dmac2 0x51>, <&dmac2 0x50>;
1293 reg = <0 0xe6e68000 0 0x40>;
1299 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1300 <&dmac2 0x53>, <&dmac2 0x52>;
1310 reg = <0 0xe6e88000 0 0x40>;
1316 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1317 <&dmac2 0x13>, <&dmac2 0x12>;
1327 reg = <0 0xe6c50000 0 0x40>;
1333 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1343 reg = <0 0xe6c40000 0 0x40>;
1349 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1359 reg = <0 0xe6f30000 0 0x40>;
1365 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1366 <&dmac2 0x5b>, <&dmac2 0x5a>;
1376 reg = <0 0xe6e90000 0 0x0064>;
1379 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1380 <&dmac2 0x41>, <&dmac2 0x40>;
1385 #size-cells = <0>;
1392 reg = <0 0xe6ea0000 0 0x0064>;
1395 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1396 <&dmac2 0x43>, <&dmac2 0x42>;
1401 #size-cells = <0>;
1408 reg = <0 0xe6c00000 0 0x0064>;
1411 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1416 #size-cells = <0>;
1423 reg = <0 0xe6c10000 0 0x0064>;
1426 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1431 #size-cells = <0>;
1437 reg = <0 0xe6ef0000 0 0x1000>;
1442 renesas,id = <0>;
1447 #size-cells = <0>;
1451 #size-cells = <0>;
1455 vin0csi20: endpoint@0 {
1456 reg = <0>;
1469 reg = <0 0xe6ef1000 0 0x1000>;
1479 #size-cells = <0>;
1483 #size-cells = <0>;
1487 vin1csi20: endpoint@0 {
1488 reg = <0>;
1501 reg = <0 0xe6ef2000 0 0x1000>;
1511 #size-cells = <0>;
1515 #size-cells = <0>;
1519 vin2csi20: endpoint@0 {
1520 reg = <0>;
1533 reg = <0 0xe6ef3000 0 0x1000>;
1543 #size-cells = <0>;
1547 #size-cells = <0>;
1551 vin3csi20: endpoint@0 {
1552 reg = <0>;
1565 reg = <0 0xe6ef4000 0 0x1000>;
1575 #size-cells = <0>;
1579 #size-cells = <0>;
1583 vin4csi20: endpoint@0 {
1584 reg = <0>;
1597 reg = <0 0xe6ef5000 0 0x1000>;
1607 #size-cells = <0>;
1611 #size-cells = <0>;
1615 vin5csi20: endpoint@0 {
1616 reg = <0>;
1629 reg = <0 0xe6ef6000 0 0x1000>;
1639 #size-cells = <0>;
1643 #size-cells = <0>;
1647 vin6csi20: endpoint@0 {
1648 reg = <0>;
1661 reg = <0 0xe6ef7000 0 0x1000>;
1671 #size-cells = <0>;
1675 #size-cells = <0>;
1679 vin7csi20: endpoint@0 {
1680 reg = <0>;
1695 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1701 * clkout : #clock-cells = <0>; <&rcar_sound>;
1705 reg = <0 0xec500000 0 0x1000>, /* SCU */
1706 <0 0xec5a0000 0 0x100>, /* ADG */
1707 <0 0xec540000 0 0x1000>, /* SSIU */
1708 <0 0xec541000 0 0x280>, /* SSI */
1709 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1732 "ssi.1", "ssi.0",
1735 "src.1", "src.0",
1736 "mix.1", "mix.0",
1737 "ctu.1", "ctu.0",
1738 "dvc.0", "dvc.1",
1750 "ssi.1", "ssi.0";
1754 ctu00: ctu-0 { };
1765 dvc0: dvc-0 {
1766 dmas = <&audma1 0xbc>;
1770 dmas = <&audma1 0xbe>;
1776 mix0: mix-0 { };
1781 src0: src-0 {
1783 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1788 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1793 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1798 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1803 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1808 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1813 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1818 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1823 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1828 dmas = <&audma0 0x97>, <&audma1 0xba>;
1834 ssi0: ssi-0 {
1836 dmas = <&audma0 0x01>, <&audma1 0x02>;
1841 dmas = <&audma0 0x03>, <&audma1 0x04>;
1846 dmas = <&audma0 0x05>, <&audma1 0x06>;
1851 dmas = <&audma0 0x07>, <&audma1 0x08>;
1856 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1861 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1866 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1871 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1876 dmas = <&audma0 0x11>, <&audma1 0x12>;
1881 dmas = <&audma0 0x13>, <&audma1 0x14>;
1887 ssiu00: ssiu-0 {
1888 dmas = <&audma0 0x15>, <&audma1 0x16>;
1892 dmas = <&audma0 0x35>, <&audma1 0x36>;
1896 dmas = <&audma0 0x37>, <&audma1 0x38>;
1900 dmas = <&audma0 0x47>, <&audma1 0x48>;
1904 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1908 dmas = <&audma0 0x43>, <&audma1 0x44>;
1912 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1916 dmas = <&audma0 0x53>, <&audma1 0x54>;
1920 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1924 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1928 dmas = <&audma0 0x57>, <&audma1 0x58>;
1932 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1936 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1940 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1944 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1948 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1952 dmas = <&audma0 0x63>, <&audma1 0x64>;
1956 dmas = <&audma0 0x67>, <&audma1 0x68>;
1960 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1964 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1968 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1972 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1976 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1980 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1984 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1988 dmas = <&audma0 0x21>, <&audma1 0x22>;
1992 dmas = <&audma0 0x23>, <&audma1 0x24>;
1996 dmas = <&audma0 0x25>, <&audma1 0x26>;
2000 dmas = <&audma0 0x27>, <&audma1 0x28>;
2004 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2008 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2012 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2016 dmas = <&audma0 0x71>, <&audma1 0x72>;
2020 dmas = <&audma0 0x17>, <&audma1 0x18>;
2024 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2028 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2032 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2036 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2040 dmas = <&audma0 0x31>, <&audma1 0x32>;
2044 dmas = <&audma0 0x33>, <&audma1 0x34>;
2048 dmas = <&audma0 0x73>, <&audma1 0x74>;
2052 dmas = <&audma0 0x75>, <&audma1 0x76>;
2056 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2060 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2064 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2068 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2072 dmas = <&audma0 0x81>, <&audma1 0x82>;
2076 dmas = <&audma0 0x83>, <&audma1 0x84>;
2080 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2084 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2088 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2092 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2101 reg = <0 0xec700000 0 0x10000>;
2130 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2143 reg = <0 0xec720000 0 0x10000>;
2185 reg = <0 0xee000000 0 0xc00>;
2196 reg = <0 0xee020000 0 0x400>;
2206 reg = <0 0xee080000 0 0x100>;
2218 reg = <0 0xee0a0000 0 0x100>;
2230 reg = <0 0xee080100 0 0x100>;
2243 reg = <0 0xee0a0100 0 0x100>;
2257 reg = <0 0xee080200 0 0x700>;
2269 reg = <0 0xee0a0200 0 0x700>;
2280 reg = <0 0xee100000 0 0x2000>;
2294 reg = <0 0xee120000 0 0x2000>;
2308 reg = <0 0xee140000 0 0x2000>;
2322 reg = <0 0xee160000 0 0x2000>;
2336 reg = <0 0xee200000 0 0x200>,
2337 <0 0x08000000 0 0x4000000>,
2338 <0 0xee208000 0 0x100>;
2345 #size-cells = <0>;
2352 #address-cells = <0>;
2354 reg = <0x0 0xf1010000 0 0x1000>,
2355 <0x0 0xf1020000 0 0x20000>,
2356 <0x0 0xf1040000 0 0x20000>,
2357 <0x0 0xf1060000 0 0x20000>;
2369 reg = <0 0xfe000000 0 0x80000>;
2372 bus-range = <0x00 0xff>;
2374 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2375 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2376 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2377 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2379 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2384 interrupt-map-mask = <0 0 0 0>;
2385 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2390 iommu-map = <0 &ipmmu_hc 0 1>;
2391 iommu-map-mask = <0>;
2398 reg = <0 0xee800000 0 0x80000>;
2401 bus-range = <0x00 0xff>;
2403 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2404 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2405 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2406 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2408 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2413 interrupt-map-mask = <0 0 0 0>;
2414 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2419 iommu-map = <0 &ipmmu_hc 1 1>;
2420 iommu-map-mask = <0>;
2427 reg = <0x0 0xfe000000 0 0x80000>,
2428 <0x0 0xfe100000 0 0x100000>,
2429 <0x0 0xfe200000 0 0x200000>,
2430 <0x0 0x30000000 0 0x8000000>,
2431 <0x0 0x38000000 0 0x8000000>;
2446 reg = <0x0 0xee800000 0 0x80000>,
2447 <0x0 0xee900000 0 0x100000>,
2448 <0x0 0xeea00000 0 0x200000>,
2449 <0x0 0xc0000000 0 0x8000000>,
2450 <0x0 0xc8000000 0 0x8000000>;
2464 reg = <0 0xfe940000 0 0x2400>;
2474 reg = <0 0xfe950000 0 0x200>;
2483 reg = <0 0xfe96f000 0 0x200>;
2492 reg = <0 0xfea27000 0 0x200>;
2501 reg = <0 0xfea2f000 0 0x200>;
2510 reg = <0 0xfea37000 0 0x200>;
2519 reg = <0 0xfe9af000 0 0x200>;
2528 reg = <0 0xfe960000 0 0x8000>;
2539 reg = <0 0xfea20000 0 0x5000>;
2550 reg = <0 0xfea28000 0 0x5000>;
2561 reg = <0 0xfea30000 0 0x5000>;
2572 reg = <0 0xfe9a0000 0 0x8000>;
2583 reg = <0 0xfea80000 0 0x10000>;
2592 #size-cells = <0>;
2594 port@0 {
2595 reg = <0>;
2600 #size-cells = <0>;
2604 csi20vin0: endpoint@0 {
2605 reg = <0>;
2642 reg = <0 0xfeaa0000 0 0x10000>;
2651 #size-cells = <0>;
2653 port@0 {
2654 reg = <0>;
2659 #size-cells = <0>;
2663 csi40vin0: endpoint@0 {
2664 reg = <0>;
2703 reg = <0 0xfead0000 0 0x10000>;
2714 #size-cells = <0>;
2715 port@0 {
2716 reg = <0>;
2733 reg = <0 0xfeb00000 0 0x70000>;
2739 clock-names = "du.0", "du.1", "du.2";
2741 reset-names = "du.0", "du.2";
2744 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2748 #size-cells = <0>;
2750 port@0 {
2751 reg = <0>;
2770 reg = <0 0xfeb90000 0 0x14>;
2778 #size-cells = <0>;
2780 port@0 {
2781 reg = <0>;
2794 reg = <0 0xfff00044 0 4>;
2803 thermal-sensors = <&tsc 0>;
2839 cooling-device = <&a57_0 0 2>;
2844 cooling-device = <&a53_0 0 2>;
2876 #clock-cells = <0>;
2877 clock-frequency = <0>;
2882 #clock-cells = <0>;
2883 clock-frequency = <0>;