Lines Matching +full:sdm845 +full:- +full:llcc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 clock-frequency = <76800000>;
37 #clock-cells = <0>;
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 clock-frequency = <32764>;
43 #clock-cells = <0>;
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 compatible = "fixed-factor-clock";
48 #clock-cells = <0>;
51 clock-mult = <1>;
52 clock-div = <2>;
55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
56 compatible = "fixed-factor-clock";
57 #clock-cells = <0>;
60 clock-mult = <1>;
61 clock-div = <2>;
66 #address-cells = <2>;
67 #size-cells = <0>;
73 enable-method = "psci";
74 next-level-cache = <&l2_0>;
75 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
76 power-domain-names = "psci", "perf";
77 cpu-idle-states = <&cluster_c4>;
79 l2_0: l2-cache {
81 cache-level = <2>;
82 cache-unified;
90 enable-method = "psci";
91 next-level-cache = <&l2_0>;
92 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
93 power-domain-names = "psci", "perf";
94 cpu-idle-states = <&cluster_c4>;
101 enable-method = "psci";
102 next-level-cache = <&l2_0>;
103 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
104 power-domain-names = "psci", "perf";
105 cpu-idle-states = <&cluster_c4>;
112 enable-method = "psci";
113 next-level-cache = <&l2_0>;
114 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
115 power-domain-names = "psci", "perf";
116 cpu-idle-states = <&cluster_c4>;
123 enable-method = "psci";
124 next-level-cache = <&l2_1>;
125 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
126 power-domain-names = "psci", "perf";
127 cpu-idle-states = <&cluster_c4>;
129 l2_1: l2-cache {
131 cache-level = <2>;
132 cache-unified;
140 enable-method = "psci";
141 next-level-cache = <&l2_1>;
142 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
143 power-domain-names = "psci", "perf";
144 cpu-idle-states = <&cluster_c4>;
151 enable-method = "psci";
152 next-level-cache = <&l2_1>;
153 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
154 power-domain-names = "psci", "perf";
155 cpu-idle-states = <&cluster_c4>;
162 enable-method = "psci";
163 next-level-cache = <&l2_1>;
164 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
165 power-domain-names = "psci", "perf";
166 cpu-idle-states = <&cluster_c4>;
173 enable-method = "psci";
174 next-level-cache = <&l2_2>;
175 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
176 power-domain-names = "psci", "perf";
177 cpu-idle-states = <&cluster_c4>;
179 l2_2: l2-cache {
181 cache-level = <2>;
182 cache-unified;
190 enable-method = "psci";
191 next-level-cache = <&l2_2>;
192 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
193 power-domain-names = "psci", "perf";
194 cpu-idle-states = <&cluster_c4>;
201 enable-method = "psci";
202 next-level-cache = <&l2_2>;
203 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
204 power-domain-names = "psci", "perf";
205 cpu-idle-states = <&cluster_c4>;
212 enable-method = "psci";
213 next-level-cache = <&l2_2>;
214 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
215 power-domain-names = "psci", "perf";
216 cpu-idle-states = <&cluster_c4>;
219 cpu-map {
275 idle-states {
276 entry-method = "psci";
278 cluster_c4: cpu-sleep-0 {
279 compatible = "arm,idle-state";
280 idle-state-name = "ret";
281 arm,psci-suspend-param = <0x00000004>;
282 entry-latency-us = <180>;
283 exit-latency-us = <500>;
284 min-residency-us = <600>;
288 domain-idle-states {
289 cluster_cl4: cluster-sleep-0 {
290 compatible = "domain-idle-state";
291 arm,psci-suspend-param = <0x01000044>;
292 entry-latency-us = <350>;
293 exit-latency-us = <500>;
294 min-residency-us = <2500>;
297 cluster_cl5: cluster-sleep-1 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x01000054>;
300 entry-latency-us = <2200>;
301 exit-latency-us = <4000>;
302 min-residency-us = <7000>;
307 dummy-sink {
308 compatible = "arm,coresight-dummy-sink";
310 in-ports {
313 remote-endpoint = <&swao_rep_out1>;
321 compatible = "qcom,scm-x1e80100", "qcom,scm";
324 qcom,dload-mode = <&tcsr 0x19000>;
330 mbox-names = "tx", "rx";
333 #address-cells = <1>;
334 #size-cells = <0>;
338 #power-domain-cells = <1>;
343 clk_virt: interconnect-0 {
344 compatible = "qcom,x1e80100-clk-virt";
345 #interconnect-cells = <2>;
346 qcom,bcm-voters = <&apps_bcm_voter>;
349 mc_virt: interconnect-1 {
350 compatible = "qcom,x1e80100-mc-virt";
351 #interconnect-cells = <2>;
352 qcom,bcm-voters = <&apps_bcm_voter>;
362 compatible = "arm,armv8-pmuv3";
367 compatible = "arm,psci-1.0";
370 cpu_pd0: power-domain-cpu0 {
371 #power-domain-cells = <0>;
372 power-domains = <&cluster_pd0>;
375 cpu_pd1: power-domain-cpu1 {
376 #power-domain-cells = <0>;
377 power-domains = <&cluster_pd0>;
380 cpu_pd2: power-domain-cpu2 {
381 #power-domain-cells = <0>;
382 power-domains = <&cluster_pd0>;
385 cpu_pd3: power-domain-cpu3 {
386 #power-domain-cells = <0>;
387 power-domains = <&cluster_pd0>;
390 cpu_pd4: power-domain-cpu4 {
391 #power-domain-cells = <0>;
392 power-domains = <&cluster_pd1>;
395 cpu_pd5: power-domain-cpu5 {
396 #power-domain-cells = <0>;
397 power-domains = <&cluster_pd1>;
400 cpu_pd6: power-domain-cpu6 {
401 #power-domain-cells = <0>;
402 power-domains = <&cluster_pd1>;
405 cpu_pd7: power-domain-cpu7 {
406 #power-domain-cells = <0>;
407 power-domains = <&cluster_pd1>;
410 cpu_pd8: power-domain-cpu8 {
411 #power-domain-cells = <0>;
412 power-domains = <&cluster_pd2>;
415 cpu_pd9: power-domain-cpu9 {
416 #power-domain-cells = <0>;
417 power-domains = <&cluster_pd2>;
420 cpu_pd10: power-domain-cpu10 {
421 #power-domain-cells = <0>;
422 power-domains = <&cluster_pd2>;
425 cpu_pd11: power-domain-cpu11 {
426 #power-domain-cells = <0>;
427 power-domains = <&cluster_pd2>;
430 cluster_pd0: power-domain-cpu-cluster0 {
431 #power-domain-cells = <0>;
432 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
433 power-domains = <&system_pd>;
436 cluster_pd1: power-domain-cpu-cluster1 {
437 #power-domain-cells = <0>;
438 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
439 power-domains = <&system_pd>;
442 cluster_pd2: power-domain-cpu-cluster2 {
443 #power-domain-cells = <0>;
444 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
445 power-domains = <&system_pd>;
448 system_pd: power-domain-system {
449 #power-domain-cells = <0>;
450 /* TODO: system-wide idle states */
454 reserved-memory {
455 #address-cells = <2>;
456 #size-cells = <2>;
459 gunyah_hyp_mem: gunyah-hyp@80000000 {
461 no-map;
464 hyp_elf_package_mem: hyp-elf-package@80800000 {
466 no-map;
471 no-map;
474 cpucp_log_mem: cpucp-log@80e00000 {
476 no-map;
481 no-map;
484 reserved-region@81380000 {
486 no-map;
489 tags_mem: tags-region@81400000 {
491 no-map;
494 xbl_dtlog_mem: xbl-dtlog@81a00000 {
496 no-map;
499 xbl_ramdump_mem: xbl-ramdump@81a40000 {
501 no-map;
504 aop_image_mem: aop-image@81c00000 {
506 no-map;
509 aop_cmd_db_mem: aop-cmd-db@81c60000 {
510 compatible = "qcom,cmd-db";
512 no-map;
515 aop_config_mem: aop-config@81c80000 {
517 no-map;
520 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
522 no-map;
525 tme_log_mem: tme-log@81ce0000 {
527 no-map;
530 uefi_log_mem: uefi-log@81ce4000 {
532 no-map;
535 secdata_apss_mem: secdata-apss@81cff000 {
537 no-map;
540 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
542 no-map;
545 gpu_prr_mem: gpu-prr@81f00000 {
547 no-map;
550 tpm_control_mem: tpm-control@81f10000 {
552 no-map;
555 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
557 no-map;
560 pld_pep_mem: pld-pep@81f30000 {
562 no-map;
565 pld_gmu_mem: pld-gmu@81f36000 {
567 no-map;
570 pld_pdp_mem: pld-pdp@81f37000 {
572 no-map;
575 tz_stat_mem: tz-stat@82700000 {
577 no-map;
580 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
582 no-map;
585 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
587 no-map;
590 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
592 no-map;
595 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
597 no-map;
600 spss_region_mem: spss-region@86700000 {
602 no-map;
605 adsp_boot_mem: adsp-boot@86b00000 {
607 no-map;
612 no-map;
617 no-map;
620 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
622 no-map;
627 no-map;
630 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
632 no-map;
635 gpu_microcode_mem: gpu-microcode@8d9fe000 {
637 no-map;
642 no-map;
647 no-map;
650 av1_encoder_mem: av1-encoder@8e900000 {
652 no-map;
655 reserved-region@8f000000 {
657 no-map;
662 no-map;
665 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
667 no-map;
670 xbl_sc_mem: xbl-sc@d8000000 {
672 no-map;
675 reserved-region@d8040000 {
677 no-map;
682 no-map;
687 no-map;
692 no-map;
695 llcc_lpi_mem: llcc-lpi@ff800000 {
697 no-map;
704 no-map;
708 qup_opp_table_100mhz: opp-table-qup100mhz {
709 compatible = "operating-points-v2";
711 opp-75000000 {
712 opp-hz = /bits/ 64 <75000000>;
713 required-opps = <&rpmhpd_opp_low_svs>;
716 opp-100000000 {
717 opp-hz = /bits/ 64 <100000000>;
718 required-opps = <&rpmhpd_opp_svs>;
722 qup_opp_table_120mhz: opp-table-qup120mhz {
723 compatible = "operating-points-v2";
725 opp-75000000 {
726 opp-hz = /bits/ 64 <75000000>;
727 required-opps = <&rpmhpd_opp_low_svs>;
730 opp-120000000 {
731 opp-hz = /bits/ 64 <120000000>;
732 required-opps = <&rpmhpd_opp_svs>;
736 smp2p-adsp {
739 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
747 qcom,local-pid = <0>;
748 qcom,remote-pid = <2>;
750 smp2p_adsp_out: master-kernel {
751 qcom,entry-name = "master-kernel";
752 #qcom,smem-state-cells = <1>;
755 smp2p_adsp_in: slave-kernel {
756 qcom,entry-name = "slave-kernel";
757 interrupt-controller;
758 #interrupt-cells = <2>;
762 smp2p-cdsp {
765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
773 qcom,local-pid = <0>;
774 qcom,remote-pid = <5>;
776 smp2p_cdsp_out: master-kernel {
777 qcom,entry-name = "master-kernel";
778 #qcom,smem-state-cells = <1>;
781 smp2p_cdsp_in: slave-kernel {
782 qcom,entry-name = "slave-kernel";
783 interrupt-controller;
784 #interrupt-cells = <2>;
789 compatible = "simple-bus";
791 #address-cells = <2>;
792 #size-cells = <2>;
793 dma-ranges = <0 0 0 0 0x10 0>;
796 gcc: clock-controller@100000 {
797 compatible = "qcom,x1e80100-gcc";
811 power-domains = <&rpmhpd RPMHPD_CX>;
812 #clock-cells = <1>;
813 #reset-cells = <1>;
814 #power-domain-cells = <1>;
818 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
822 interrupt-controller;
823 #interrupt-cells = <3>;
825 #mbox-cells = <2>;
828 gpi_dma2: dma-controller@800000 {
829 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
845 dma-channels = <12>;
846 dma-channel-mask = <0x3e>;
847 #dma-cells = <3>;
855 compatible = "qcom,geni-se-qup";
860 clock-names = "m-ahb",
861 "s-ahb";
865 #address-cells = <2>;
866 #size-cells = <2>;
872 compatible = "qcom,geni-i2c";
878 clock-names = "se";
886 interconnect-names = "qup-core",
887 "qup-config",
888 "qup-memory";
890 power-domains = <&rpmhpd RPMHPD_CX>;
891 required-opps = <&rpmhpd_opp_low_svs>;
895 dma-names = "tx",
898 pinctrl-0 = <&qup_i2c16_data_clk>;
899 pinctrl-names = "default";
901 #address-cells = <1>;
902 #size-cells = <0>;
908 compatible = "qcom,geni-spi";
914 clock-names = "se";
922 interconnect-names = "qup-core",
923 "qup-config",
924 "qup-memory";
926 power-domains = <&rpmhpd RPMHPD_CX>;
927 operating-points-v2 = <&qup_opp_table_120mhz>;
931 dma-names = "tx",
934 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
935 pinctrl-names = "default";
937 #address-cells = <1>;
938 #size-cells = <0>;
944 compatible = "qcom,geni-i2c";
950 clock-names = "se";
958 interconnect-names = "qup-core",
959 "qup-config",
960 "qup-memory";
962 power-domains = <&rpmhpd RPMHPD_CX>;
963 required-opps = <&rpmhpd_opp_low_svs>;
967 dma-names = "tx",
970 pinctrl-0 = <&qup_i2c17_data_clk>;
971 pinctrl-names = "default";
973 #address-cells = <1>;
974 #size-cells = <0>;
980 compatible = "qcom,geni-spi";
986 clock-names = "se";
994 interconnect-names = "qup-core",
995 "qup-config",
996 "qup-memory";
998 power-domains = <&rpmhpd RPMHPD_CX>;
999 operating-points-v2 = <&qup_opp_table_120mhz>;
1003 dma-names = "tx",
1006 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1007 pinctrl-names = "default";
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1016 compatible = "qcom,geni-i2c";
1022 clock-names = "se";
1030 interconnect-names = "qup-core",
1031 "qup-config",
1032 "qup-memory";
1034 power-domains = <&rpmhpd RPMHPD_CX>;
1035 required-opps = <&rpmhpd_opp_low_svs>;
1039 dma-names = "tx",
1042 pinctrl-0 = <&qup_i2c18_data_clk>;
1043 pinctrl-names = "default";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1052 compatible = "qcom,geni-spi";
1058 clock-names = "se";
1066 interconnect-names = "qup-core",
1067 "qup-config",
1068 "qup-memory";
1070 power-domains = <&rpmhpd RPMHPD_CX>;
1071 operating-points-v2 = <&qup_opp_table_100mhz>;
1075 dma-names = "tx",
1078 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1079 pinctrl-names = "default";
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1088 compatible = "qcom,geni-i2c";
1094 clock-names = "se";
1102 interconnect-names = "qup-core",
1103 "qup-config",
1104 "qup-memory";
1106 power-domains = <&rpmhpd RPMHPD_CX>;
1107 required-opps = <&rpmhpd_opp_low_svs>;
1111 dma-names = "tx",
1114 pinctrl-0 = <&qup_i2c19_data_clk>;
1115 pinctrl-names = "default";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1124 compatible = "qcom,geni-spi";
1130 clock-names = "se";
1138 interconnect-names = "qup-core",
1139 "qup-config",
1140 "qup-memory";
1142 power-domains = <&rpmhpd RPMHPD_CX>;
1143 operating-points-v2 = <&qup_opp_table_100mhz>;
1147 dma-names = "tx",
1150 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1151 pinctrl-names = "default";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1160 compatible = "qcom,geni-i2c";
1166 clock-names = "se";
1174 interconnect-names = "qup-core",
1175 "qup-config",
1176 "qup-memory";
1178 power-domains = <&rpmhpd RPMHPD_CX>;
1179 required-opps = <&rpmhpd_opp_low_svs>;
1183 dma-names = "tx",
1186 pinctrl-0 = <&qup_i2c20_data_clk>;
1187 pinctrl-names = "default";
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1196 compatible = "qcom,geni-spi";
1202 clock-names = "se";
1210 interconnect-names = "qup-core",
1211 "qup-config",
1212 "qup-memory";
1214 power-domains = <&rpmhpd RPMHPD_CX>;
1215 operating-points-v2 = <&qup_opp_table_100mhz>;
1219 dma-names = "tx",
1222 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1223 pinctrl-names = "default";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1232 compatible = "qcom,geni-i2c";
1238 clock-names = "se";
1246 interconnect-names = "qup-core",
1247 "qup-config",
1248 "qup-memory";
1250 power-domains = <&rpmhpd RPMHPD_CX>;
1251 required-opps = <&rpmhpd_opp_low_svs>;
1255 dma-names = "tx",
1258 pinctrl-0 = <&qup_i2c21_data_clk>;
1259 pinctrl-names = "default";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1268 compatible = "qcom,geni-spi";
1274 clock-names = "se";
1282 interconnect-names = "qup-core",
1283 "qup-config",
1284 "qup-memory";
1286 power-domains = <&rpmhpd RPMHPD_CX>;
1287 operating-points-v2 = <&qup_opp_table_100mhz>;
1291 dma-names = "tx",
1294 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1295 pinctrl-names = "default";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1304 compatible = "qcom,geni-uart";
1310 clock-names = "se";
1316 interconnect-names = "qup-core",
1317 "qup-config";
1319 power-domains = <&rpmhpd RPMHPD_CX>;
1320 operating-points-v2 = <&qup_opp_table_100mhz>;
1322 pinctrl-0 = <&qup_uart21_default>;
1323 pinctrl-names = "default";
1329 compatible = "qcom,geni-i2c";
1335 clock-names = "se";
1343 interconnect-names = "qup-core",
1344 "qup-config",
1345 "qup-memory";
1347 power-domains = <&rpmhpd RPMHPD_CX>;
1348 required-opps = <&rpmhpd_opp_low_svs>;
1352 dma-names = "tx",
1355 pinctrl-0 = <&qup_i2c22_data_clk>;
1356 pinctrl-names = "default";
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1365 compatible = "qcom,geni-spi";
1371 clock-names = "se";
1379 interconnect-names = "qup-core",
1380 "qup-config",
1381 "qup-memory";
1383 power-domains = <&rpmhpd RPMHPD_CX>;
1384 operating-points-v2 = <&qup_opp_table_100mhz>;
1388 dma-names = "tx",
1391 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1392 pinctrl-names = "default";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1401 compatible = "qcom,geni-i2c";
1407 clock-names = "se";
1415 interconnect-names = "qup-core",
1416 "qup-config",
1417 "qup-memory";
1419 power-domains = <&rpmhpd RPMHPD_CX>;
1420 required-opps = <&rpmhpd_opp_low_svs>;
1424 dma-names = "tx",
1427 pinctrl-0 = <&qup_i2c23_data_clk>;
1428 pinctrl-names = "default";
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1437 compatible = "qcom,geni-spi";
1443 clock-names = "se";
1451 interconnect-names = "qup-core",
1452 "qup-config",
1453 "qup-memory";
1455 power-domains = <&rpmhpd RPMHPD_CX>;
1456 operating-points-v2 = <&qup_opp_table_100mhz>;
1460 dma-names = "tx",
1463 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1464 pinctrl-names = "default";
1466 #address-cells = <1>;
1467 #size-cells = <0>;
1473 gpi_dma1: dma-controller@a00000 {
1474 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1490 dma-channels = <12>;
1491 dma-channel-mask = <0x3e>;
1492 #dma-cells = <3>;
1500 compatible = "qcom,geni-se-qup";
1505 clock-names = "m-ahb",
1506 "s-ahb";
1510 #address-cells = <2>;
1511 #size-cells = <2>;
1517 compatible = "qcom,geni-i2c";
1523 clock-names = "se";
1531 interconnect-names = "qup-core",
1532 "qup-config",
1533 "qup-memory";
1535 power-domains = <&rpmhpd RPMHPD_CX>;
1536 required-opps = <&rpmhpd_opp_low_svs>;
1540 dma-names = "tx",
1543 pinctrl-0 = <&qup_i2c8_data_clk>;
1544 pinctrl-names = "default";
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1553 compatible = "qcom,geni-spi";
1559 clock-names = "se";
1567 interconnect-names = "qup-core",
1568 "qup-config",
1569 "qup-memory";
1571 power-domains = <&rpmhpd RPMHPD_CX>;
1572 operating-points-v2 = <&qup_opp_table_120mhz>;
1576 dma-names = "tx",
1579 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1580 pinctrl-names = "default";
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1589 compatible = "qcom,geni-i2c";
1595 clock-names = "se";
1603 interconnect-names = "qup-core",
1604 "qup-config",
1605 "qup-memory";
1607 power-domains = <&rpmhpd RPMHPD_CX>;
1608 required-opps = <&rpmhpd_opp_low_svs>;
1612 dma-names = "tx",
1615 pinctrl-0 = <&qup_i2c9_data_clk>;
1616 pinctrl-names = "default";
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1625 compatible = "qcom,geni-spi";
1631 clock-names = "se";
1639 interconnect-names = "qup-core",
1640 "qup-config",
1641 "qup-memory";
1643 power-domains = <&rpmhpd RPMHPD_CX>;
1644 operating-points-v2 = <&qup_opp_table_120mhz>;
1648 dma-names = "tx",
1651 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1652 pinctrl-names = "default";
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1661 compatible = "qcom,geni-i2c";
1667 clock-names = "se";
1675 interconnect-names = "qup-core",
1676 "qup-config",
1677 "qup-memory";
1679 power-domains = <&rpmhpd RPMHPD_CX>;
1680 required-opps = <&rpmhpd_opp_low_svs>;
1684 dma-names = "tx",
1687 pinctrl-0 = <&qup_i2c10_data_clk>;
1688 pinctrl-names = "default";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1697 compatible = "qcom,geni-spi";
1703 clock-names = "se";
1711 interconnect-names = "qup-core",
1712 "qup-config",
1713 "qup-memory";
1715 power-domains = <&rpmhpd RPMHPD_CX>;
1716 operating-points-v2 = <&qup_opp_table_100mhz>;
1720 dma-names = "tx",
1723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1724 pinctrl-names = "default";
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1733 compatible = "qcom,geni-i2c";
1739 clock-names = "se";
1747 interconnect-names = "qup-core",
1748 "qup-config",
1749 "qup-memory";
1751 power-domains = <&rpmhpd RPMHPD_CX>;
1752 required-opps = <&rpmhpd_opp_low_svs>;
1756 dma-names = "tx",
1759 pinctrl-0 = <&qup_i2c11_data_clk>;
1760 pinctrl-names = "default";
1762 #address-cells = <1>;
1763 #size-cells = <0>;
1769 compatible = "qcom,geni-spi";
1775 clock-names = "se";
1783 interconnect-names = "qup-core",
1784 "qup-config",
1785 "qup-memory";
1787 power-domains = <&rpmhpd RPMHPD_CX>;
1788 operating-points-v2 = <&qup_opp_table_100mhz>;
1792 dma-names = "tx",
1795 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1796 pinctrl-names = "default";
1798 #address-cells = <1>;
1799 #size-cells = <0>;
1805 compatible = "qcom,geni-i2c";
1811 clock-names = "se";
1819 interconnect-names = "qup-core",
1820 "qup-config",
1821 "qup-memory";
1823 power-domains = <&rpmhpd RPMHPD_CX>;
1824 required-opps = <&rpmhpd_opp_low_svs>;
1828 dma-names = "tx",
1831 pinctrl-0 = <&qup_i2c12_data_clk>;
1832 pinctrl-names = "default";
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1841 compatible = "qcom,geni-spi";
1847 clock-names = "se";
1855 interconnect-names = "qup-core",
1856 "qup-config",
1857 "qup-memory";
1859 power-domains = <&rpmhpd RPMHPD_CX>;
1860 operating-points-v2 = <&qup_opp_table_100mhz>;
1864 dma-names = "tx",
1867 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1868 pinctrl-names = "default";
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1877 compatible = "qcom,geni-i2c";
1883 clock-names = "se";
1891 interconnect-names = "qup-core",
1892 "qup-config",
1893 "qup-memory";
1895 power-domains = <&rpmhpd RPMHPD_CX>;
1896 required-opps = <&rpmhpd_opp_low_svs>;
1900 dma-names = "tx",
1903 pinctrl-0 = <&qup_i2c13_data_clk>;
1904 pinctrl-names = "default";
1906 #address-cells = <1>;
1907 #size-cells = <0>;
1913 compatible = "qcom,geni-spi";
1919 clock-names = "se";
1927 interconnect-names = "qup-core",
1928 "qup-config",
1929 "qup-memory";
1931 power-domains = <&rpmhpd RPMHPD_CX>;
1932 operating-points-v2 = <&qup_opp_table_100mhz>;
1936 dma-names = "tx",
1939 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1940 pinctrl-names = "default";
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1949 compatible = "qcom,geni-i2c";
1955 clock-names = "se";
1963 interconnect-names = "qup-core",
1964 "qup-config",
1965 "qup-memory";
1967 power-domains = <&rpmhpd RPMHPD_CX>;
1968 required-opps = <&rpmhpd_opp_low_svs>;
1972 dma-names = "tx",
1975 pinctrl-0 = <&qup_i2c14_data_clk>;
1976 pinctrl-names = "default";
1978 #address-cells = <1>;
1979 #size-cells = <0>;
1985 compatible = "qcom,geni-spi";
1991 clock-names = "se";
1999 interconnect-names = "qup-core",
2000 "qup-config",
2001 "qup-memory";
2003 power-domains = <&rpmhpd RPMHPD_CX>;
2004 operating-points-v2 = <&qup_opp_table_100mhz>;
2008 dma-names = "tx",
2011 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2012 pinctrl-names = "default";
2014 #address-cells = <1>;
2015 #size-cells = <0>;
2021 compatible = "qcom,geni-uart";
2027 clock-names = "se";
2033 interconnect-names = "qup-core",
2034 "qup-config";
2036 power-domains = <&rpmhpd RPMHPD_CX>;
2037 operating-points-v2 = <&qup_opp_table_100mhz>;
2039 pinctrl-0 = <&qup_uart14_default>;
2040 pinctrl-names = "default";
2046 compatible = "qcom,geni-i2c";
2052 clock-names = "se";
2060 interconnect-names = "qup-core",
2061 "qup-config",
2062 "qup-memory";
2064 power-domains = <&rpmhpd RPMHPD_CX>;
2065 required-opps = <&rpmhpd_opp_low_svs>;
2069 dma-names = "tx",
2072 pinctrl-0 = <&qup_i2c15_data_clk>;
2073 pinctrl-names = "default";
2075 #address-cells = <1>;
2076 #size-cells = <0>;
2082 compatible = "qcom,geni-spi";
2088 clock-names = "se";
2096 interconnect-names = "qup-core",
2097 "qup-config",
2098 "qup-memory";
2100 power-domains = <&rpmhpd RPMHPD_CX>;
2101 operating-points-v2 = <&qup_opp_table_100mhz>;
2105 dma-names = "tx",
2108 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2109 pinctrl-names = "default";
2111 #address-cells = <1>;
2112 #size-cells = <0>;
2118 gpi_dma0: dma-controller@b00000 {
2119 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
2135 dma-channels = <12>;
2136 dma-channel-mask = <0x3e>;
2137 #dma-cells = <3>;
2145 compatible = "qcom,geni-se-qup";
2150 clock-names = "m-ahb",
2151 "s-ahb";
2154 #address-cells = <2>;
2155 #size-cells = <2>;
2161 compatible = "qcom,geni-i2c";
2167 clock-names = "se";
2175 interconnect-names = "qup-core",
2176 "qup-config",
2177 "qup-memory";
2179 power-domains = <&rpmhpd RPMHPD_CX>;
2180 required-opps = <&rpmhpd_opp_low_svs>;
2184 dma-names = "tx",
2187 pinctrl-0 = <&qup_i2c0_data_clk>;
2188 pinctrl-names = "default";
2190 #address-cells = <1>;
2191 #size-cells = <0>;
2197 compatible = "qcom,geni-spi";
2203 clock-names = "se";
2211 interconnect-names = "qup-core",
2212 "qup-config",
2213 "qup-memory";
2215 power-domains = <&rpmhpd RPMHPD_CX>;
2216 operating-points-v2 = <&qup_opp_table_120mhz>;
2220 dma-names = "tx",
2223 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2224 pinctrl-names = "default";
2226 #address-cells = <1>;
2227 #size-cells = <0>;
2233 compatible = "qcom,geni-i2c";
2239 clock-names = "se";
2247 interconnect-names = "qup-core",
2248 "qup-config",
2249 "qup-memory";
2251 power-domains = <&rpmhpd RPMHPD_CX>;
2252 required-opps = <&rpmhpd_opp_low_svs>;
2256 dma-names = "tx",
2259 pinctrl-0 = <&qup_i2c1_data_clk>;
2260 pinctrl-names = "default";
2262 #address-cells = <1>;
2263 #size-cells = <0>;
2269 compatible = "qcom,geni-spi";
2275 clock-names = "se";
2283 interconnect-names = "qup-core",
2284 "qup-config",
2285 "qup-memory";
2287 power-domains = <&rpmhpd RPMHPD_CX>;
2288 operating-points-v2 = <&qup_opp_table_120mhz>;
2292 dma-names = "tx",
2295 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2296 pinctrl-names = "default";
2298 #address-cells = <1>;
2299 #size-cells = <0>;
2305 compatible = "qcom,geni-i2c";
2311 clock-names = "se";
2319 interconnect-names = "qup-core",
2320 "qup-config",
2321 "qup-memory";
2323 power-domains = <&rpmhpd RPMHPD_CX>;
2324 required-opps = <&rpmhpd_opp_low_svs>;
2328 dma-names = "tx",
2331 pinctrl-0 = <&qup_i2c2_data_clk>;
2332 pinctrl-names = "default";
2334 #address-cells = <1>;
2335 #size-cells = <0>;
2341 compatible = "qcom,geni-uart";
2347 clock-names = "se";
2353 interconnect-names = "qup-core",
2354 "qup-config";
2356 power-domains = <&rpmhpd RPMHPD_CX>;
2357 operating-points-v2 = <&qup_opp_table_100mhz>;
2359 pinctrl-0 = <&qup_uart2_default>;
2360 pinctrl-names = "default";
2366 compatible = "qcom,geni-spi";
2372 clock-names = "se";
2380 interconnect-names = "qup-core",
2381 "qup-config",
2382 "qup-memory";
2384 power-domains = <&rpmhpd RPMHPD_CX>;
2385 operating-points-v2 = <&qup_opp_table_100mhz>;
2389 dma-names = "tx",
2392 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2393 pinctrl-names = "default";
2395 #address-cells = <1>;
2396 #size-cells = <0>;
2402 compatible = "qcom,geni-i2c";
2408 clock-names = "se";
2416 interconnect-names = "qup-core",
2417 "qup-config",
2418 "qup-memory";
2420 power-domains = <&rpmhpd RPMHPD_CX>;
2421 required-opps = <&rpmhpd_opp_low_svs>;
2425 dma-names = "tx",
2428 pinctrl-0 = <&qup_i2c3_data_clk>;
2429 pinctrl-names = "default";
2431 #address-cells = <1>;
2432 #size-cells = <0>;
2438 compatible = "qcom,geni-spi";
2444 clock-names = "se";
2452 interconnect-names = "qup-core",
2453 "qup-config",
2454 "qup-memory";
2456 power-domains = <&rpmhpd RPMHPD_CX>;
2457 operating-points-v2 = <&qup_opp_table_100mhz>;
2461 dma-names = "tx",
2464 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2465 pinctrl-names = "default";
2467 #address-cells = <1>;
2468 #size-cells = <0>;
2474 compatible = "qcom,geni-i2c";
2480 clock-names = "se";
2488 interconnect-names = "qup-core",
2489 "qup-config",
2490 "qup-memory";
2492 power-domains = <&rpmhpd RPMHPD_CX>;
2493 required-opps = <&rpmhpd_opp_low_svs>;
2497 dma-names = "tx",
2500 pinctrl-0 = <&qup_i2c4_data_clk>;
2501 pinctrl-names = "default";
2503 #address-cells = <1>;
2504 #size-cells = <0>;
2510 compatible = "qcom,geni-spi";
2516 clock-names = "se";
2524 interconnect-names = "qup-core",
2525 "qup-config",
2526 "qup-memory";
2528 power-domains = <&rpmhpd RPMHPD_CX>;
2529 operating-points-v2 = <&qup_opp_table_100mhz>;
2533 dma-names = "tx",
2536 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2537 pinctrl-names = "default";
2539 #address-cells = <1>;
2540 #size-cells = <0>;
2546 compatible = "qcom,geni-i2c";
2552 clock-names = "se";
2560 interconnect-names = "qup-core",
2561 "qup-config",
2562 "qup-memory";
2564 power-domains = <&rpmhpd RPMHPD_CX>;
2565 required-opps = <&rpmhpd_opp_low_svs>;
2569 dma-names = "tx",
2572 pinctrl-0 = <&qup_i2c5_data_clk>;
2573 pinctrl-names = "default";
2575 #address-cells = <1>;
2576 #size-cells = <0>;
2582 compatible = "qcom,geni-spi";
2588 clock-names = "se";
2596 interconnect-names = "qup-core",
2597 "qup-config",
2598 "qup-memory";
2600 power-domains = <&rpmhpd RPMHPD_CX>;
2601 operating-points-v2 = <&qup_opp_table_100mhz>;
2605 dma-names = "tx",
2608 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2609 pinctrl-names = "default";
2611 #address-cells = <1>;
2612 #size-cells = <0>;
2618 compatible = "qcom,geni-i2c";
2624 clock-names = "se";
2632 interconnect-names = "qup-core",
2633 "qup-config",
2634 "qup-memory";
2636 power-domains = <&rpmhpd RPMHPD_CX>;
2637 required-opps = <&rpmhpd_opp_low_svs>;
2641 dma-names = "tx",
2644 pinctrl-0 = <&qup_i2c6_data_clk>;
2645 pinctrl-names = "default";
2647 #address-cells = <1>;
2648 #size-cells = <0>;
2654 compatible = "qcom,geni-spi";
2660 clock-names = "se";
2668 interconnect-names = "qup-core",
2669 "qup-config",
2670 "qup-memory";
2672 power-domains = <&rpmhpd RPMHPD_CX>;
2673 operating-points-v2 = <&qup_opp_table_100mhz>;
2677 dma-names = "tx",
2680 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2681 pinctrl-names = "default";
2683 #address-cells = <1>;
2684 #size-cells = <0>;
2690 compatible = "qcom,geni-i2c";
2696 clock-names = "se";
2704 interconnect-names = "qup-core",
2705 "qup-config",
2706 "qup-memory";
2708 power-domains = <&rpmhpd RPMHPD_CX>;
2709 required-opps = <&rpmhpd_opp_low_svs>;
2713 dma-names = "tx",
2716 pinctrl-0 = <&qup_i2c7_data_clk>;
2717 pinctrl-names = "default";
2719 #address-cells = <1>;
2720 #size-cells = <0>;
2726 compatible = "qcom,geni-spi";
2732 clock-names = "se";
2740 interconnect-names = "qup-core",
2741 "qup-config",
2742 "qup-memory";
2744 power-domains = <&rpmhpd RPMHPD_CX>;
2745 operating-points-v2 = <&qup_opp_table_100mhz>;
2749 dma-names = "tx",
2752 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2753 pinctrl-names = "default";
2755 #address-cells = <1>;
2756 #size-cells = <0>;
2762 tsens0: thermal-sensor@c271000 {
2763 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2767 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2769 interrupt-names = "uplow",
2774 #thermal-sensor-cells = <1>;
2777 tsens1: thermal-sensor@c272000 {
2778 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2782 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2784 interrupt-names = "uplow",
2789 #thermal-sensor-cells = <1>;
2792 tsens2: thermal-sensor@c273000 {
2793 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2797 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2799 interrupt-names = "uplow",
2804 #thermal-sensor-cells = <1>;
2807 tsens3: thermal-sensor@c274000 {
2808 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2812 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2814 interrupt-names = "uplow",
2819 #thermal-sensor-cells = <1>;
2823 compatible = "qcom,x1e80100-snps-eusb2-phy",
2824 "qcom,sm8550-snps-eusb2-phy";
2826 #phy-cells = <0>;
2829 clock-names = "ref";
2837 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2844 clock-names = "aux",
2849 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2853 reset-names = "phy",
2856 #clock-cells = <1>;
2857 #phy-cells = <1>;
2859 orientation-switch;
2864 #address-cells = <1>;
2865 #size-cells = <0>;
2878 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2886 remote-endpoint = <&mdss_dp0_out>;
2893 compatible = "qcom,x1e80100-snps-eusb2-phy",
2894 "qcom,sm8550-snps-eusb2-phy";
2896 #phy-cells = <0>;
2899 clock-names = "ref";
2907 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2914 clock-names = "aux",
2919 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2923 reset-names = "phy",
2926 #clock-cells = <1>;
2927 #phy-cells = <1>;
2929 orientation-switch;
2934 #address-cells = <1>;
2935 #size-cells = <0>;
2948 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2956 remote-endpoint = <&mdss_dp1_out>;
2963 compatible = "qcom,x1e80100-snps-eusb2-phy",
2964 "qcom,sm8550-snps-eusb2-phy";
2966 #phy-cells = <0>;
2969 clock-names = "ref";
2977 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2984 clock-names = "aux",
2989 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2993 reset-names = "phy",
2996 #clock-cells = <1>;
2997 #phy-cells = <1>;
2999 orientation-switch;
3004 #address-cells = <1>;
3005 #size-cells = <0>;
3018 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
3026 remote-endpoint = <&mdss_dp2_out>;
3033 compatible = "qcom,x1e80100-cnoc-main";
3036 qcom,bcm-voters = <&apps_bcm_voter>;
3038 #interconnect-cells = <2>;
3042 compatible = "qcom,x1e80100-cnoc-cfg";
3045 qcom,bcm-voters = <&apps_bcm_voter>;
3047 #interconnect-cells = <2>;
3051 compatible = "qcom,x1e80100-system-noc";
3054 qcom,bcm-voters = <&apps_bcm_voter>;
3056 #interconnect-cells = <2>;
3060 compatible = "qcom,x1e80100-pcie-south-anoc";
3063 qcom,bcm-voters = <&apps_bcm_voter>;
3065 #interconnect-cells = <2>;
3069 compatible = "qcom,x1e80100-pcie-center-anoc";
3072 qcom,bcm-voters = <&apps_bcm_voter>;
3074 #interconnect-cells = <2>;
3078 compatible = "qcom,x1e80100-aggre1-noc";
3081 qcom,bcm-voters = <&apps_bcm_voter>;
3083 #interconnect-cells = <2>;
3087 compatible = "qcom,x1e80100-aggre2-noc";
3090 qcom,bcm-voters = <&apps_bcm_voter>;
3092 #interconnect-cells = <2>;
3096 compatible = "qcom,x1e80100-pcie-north-anoc";
3099 qcom,bcm-voters = <&apps_bcm_voter>;
3101 #interconnect-cells = <2>;
3105 compatible = "qcom,x1e80100-usb-center-anoc";
3108 qcom,bcm-voters = <&apps_bcm_voter>;
3110 #interconnect-cells = <2>;
3114 compatible = "qcom,x1e80100-usb-north-anoc";
3117 qcom,bcm-voters = <&apps_bcm_voter>;
3119 #interconnect-cells = <2>;
3123 compatible = "qcom,x1e80100-usb-south-anoc";
3126 qcom,bcm-voters = <&apps_bcm_voter>;
3128 #interconnect-cells = <2>;
3132 compatible = "qcom,x1e80100-mmss-noc";
3135 qcom,bcm-voters = <&apps_bcm_voter>;
3137 #interconnect-cells = <2>;
3142 compatible = "qcom,pcie-x1e80100";
3149 reg-names = "parf",
3155 #address-cells = <3>;
3156 #size-cells = <2>;
3160 bus-range = <0x00 0xff>;
3162 dma-coherent;
3164 linux,pci-domain = <3>;
3165 num-lanes = <8>;
3176 interrupt-names = "msi0",
3186 #interrupt-cells = <1>;
3187 interrupt-map-mask = <0 0 0 0x7>;
3188 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3200 clock-names = "aux",
3208 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
3209 assigned-clock-rates = <19200000>;
3215 interconnect-names = "pcie-mem",
3216 "cpu-pcie";
3220 reset-names = "pci",
3223 power-domains = <&gcc GCC_PCIE_3_GDSC>;
3226 phy-names = "pciephy";
3228 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
3230 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
3232 operating-points-v2 = <&pcie3_opp_table>;
3236 pcie3_opp_table: opp-table {
3237 compatible = "operating-points-v2";
3240 opp-2500000 {
3241 opp-hz = /bits/ 64 <2500000>;
3242 required-opps = <&rpmhpd_opp_low_svs>;
3243 opp-peak-kBps = <250000 1>;
3247 opp-5000000 {
3248 opp-hz = /bits/ 64 <5000000>;
3249 required-opps = <&rpmhpd_opp_low_svs>;
3250 opp-peak-kBps = <500000 1>;
3254 opp-10000000 {
3255 opp-hz = /bits/ 64 <10000000>;
3256 required-opps = <&rpmhpd_opp_low_svs>;
3257 opp-peak-kBps = <1000000 1>;
3261 opp-20000000 {
3262 opp-hz = /bits/ 64 <20000000>;
3263 required-opps = <&rpmhpd_opp_low_svs>;
3264 opp-peak-kBps = <2000000 1>;
3268 opp-40000000 {
3269 opp-hz = /bits/ 64 <40000000>;
3270 required-opps = <&rpmhpd_opp_low_svs>;
3271 opp-peak-kBps = <4000000 1>;
3275 opp-8000000 {
3276 opp-hz = /bits/ 64 <8000000>;
3277 required-opps = <&rpmhpd_opp_svs>;
3278 opp-peak-kBps = <984500 1>;
3282 opp-16000000 {
3283 opp-hz = /bits/ 64 <16000000>;
3284 required-opps = <&rpmhpd_opp_svs>;
3285 opp-peak-kBps = <1969000 1>;
3289 opp-32000000 {
3290 opp-hz = /bits/ 64 <32000000>;
3291 required-opps = <&rpmhpd_opp_svs>;
3292 opp-peak-kBps = <3938000 1>;
3296 opp-64000000 {
3297 opp-hz = /bits/ 64 <64000000>;
3298 required-opps = <&rpmhpd_opp_svs>;
3299 opp-peak-kBps = <7876000 1>;
3303 opp-128000000 {
3304 opp-hz = /bits/ 64 <128000000>;
3305 required-opps = <&rpmhpd_opp_svs>;
3306 opp-peak-kBps = <15753000 1>;
3312 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
3321 clock-names = "aux",
3330 reset-names = "phy",
3333 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
3334 assigned-clock-rates = <100000000>;
3336 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
3338 #clock-cells = <0>;
3339 clock-output-names = "pcie3_pipe_clk";
3341 #phy-cells = <0>;
3348 compatible = "qcom,pcie-x1e80100";
3355 reg-names = "parf",
3361 #address-cells = <3>;
3362 #size-cells = <2>;
3365 bus-range = <0x00 0xff>;
3367 dma-coherent;
3369 linux,pci-domain = <6>;
3370 num-lanes = <4>;
3372 msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3383 interrupt-names = "msi0",
3393 #interrupt-cells = <1>;
3394 interrupt-map-mask = <0 0 0 0x7>;
3395 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
3407 clock-names = "aux",
3415 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
3416 assigned-clock-rates = <19200000>;
3422 interconnect-names = "pcie-mem",
3423 "cpu-pcie";
3427 reset-names = "pci",
3430 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
3431 required-opps = <&rpmhpd_opp_nom>;
3434 phy-names = "pciephy";
3436 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
3437 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
3443 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3453 clock-names = "aux",
3462 reset-names = "phy",
3465 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3466 assigned-clock-rates = <100000000>;
3468 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3470 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3472 #clock-cells = <0>;
3473 clock-output-names = "pcie6a_pipe_clk";
3475 #phy-cells = <0>;
3482 compatible = "qcom,pcie-x1e80100";
3489 reg-names = "parf",
3495 #address-cells = <3>;
3496 #size-cells = <2>;
3499 bus-range = <0x00 0xff>;
3501 dma-coherent;
3503 linux,pci-domain = <5>;
3504 num-lanes = <2>;
3515 interrupt-names = "msi0",
3525 #interrupt-cells = <1>;
3526 interrupt-map-mask = <0 0 0 0x7>;
3527 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3539 clock-names = "aux",
3547 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3548 assigned-clock-rates = <19200000>;
3554 interconnect-names = "pcie-mem",
3555 "cpu-pcie";
3559 reset-names = "pci",
3562 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3563 required-opps = <&rpmhpd_opp_nom>;
3566 phy-names = "pciephy";
3568 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3574 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3583 clock-names = "aux",
3592 reset-names = "phy",
3595 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3596 assigned-clock-rates = <100000000>;
3598 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3600 #clock-cells = <0>;
3601 clock-output-names = "pcie5_pipe_clk";
3603 #phy-cells = <0>;
3610 compatible = "qcom,pcie-x1e80100";
3617 reg-names = "parf",
3623 #address-cells = <3>;
3624 #size-cells = <2>;
3627 bus-range = <0x00 0xff>;
3629 dma-coherent;
3631 linux,pci-domain = <4>;
3632 num-lanes = <2>;
3634 msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3645 interrupt-names = "msi0",
3655 #interrupt-cells = <1>;
3656 interrupt-map-mask = <0 0 0 0x7>;
3657 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3669 clock-names = "aux",
3677 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3678 assigned-clock-rates = <19200000>;
3684 interconnect-names = "pcie-mem",
3685 "cpu-pcie";
3689 reset-names = "pci",
3692 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3693 required-opps = <&rpmhpd_opp_nom>;
3696 phy-names = "pciephy";
3698 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3705 bus-range = <0x01 0xff>;
3707 #address-cells = <3>;
3708 #size-cells = <2>;
3714 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3723 clock-names = "aux",
3732 reset-names = "phy",
3735 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3736 assigned-clock-rates = <100000000>;
3738 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3740 #clock-cells = <0>;
3741 clock-output-names = "pcie4_pipe_clk";
3743 #phy-cells = <0>;
3749 compatible = "qcom,tcsr-mutex";
3751 #hwlock-cells = <1>;
3754 tcsr: clock-controller@1fc0000 {
3755 compatible = "qcom,x1e80100-tcsr", "syscon";
3758 #clock-cells = <1>;
3759 #reset-cells = <1>;
3763 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3768 reg-names = "kgsl_3d0_reg_memory",
3777 operating-points-v2 = <&gpu_opp_table>;
3780 #cooling-cells = <2>;
3783 interconnect-names = "gfx-mem";
3787 gpu_zap_shader: zap-shader {
3788 memory-region = <&gpu_microcode_mem>;
3791 gpu_opp_table: opp-table {
3792 compatible = "operating-points-v2-adreno", "operating-points-v2";
3794 opp-1250000000 {
3795 opp-hz = /bits/ 64 <1250000000>;
3796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
3797 opp-peak-kBps = <16500000>;
3798 qcom,opp-acd-level = <0xa82a5ffd>;
3801 opp-1175000000 {
3802 opp-hz = /bits/ 64 <1175000000>;
3803 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
3804 opp-peak-kBps = <14398438>;
3805 qcom,opp-acd-level = <0xa82a5ffd>;
3808 opp-1100000000 {
3809 opp-hz = /bits/ 64 <1100000000>;
3810 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3811 opp-peak-kBps = <14398438>;
3812 qcom,opp-acd-level = <0xa82a5ffd>;
3815 opp-1000000000 {
3816 opp-hz = /bits/ 64 <1000000000>;
3817 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3818 opp-peak-kBps = <14398438>;
3819 qcom,opp-acd-level = <0xa82b5ffd>;
3822 opp-925000000 {
3823 opp-hz = /bits/ 64 <925000000>;
3824 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3825 opp-peak-kBps = <14398438>;
3826 qcom,opp-acd-level = <0xa82b5ffd>;
3829 opp-800000000 {
3830 opp-hz = /bits/ 64 <800000000>;
3831 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3832 opp-peak-kBps = <12449219>;
3833 qcom,opp-acd-level = <0xa82c5ffd>;
3836 opp-744000000 {
3837 opp-hz = /bits/ 64 <744000000>;
3838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3839 opp-peak-kBps = <10687500>;
3840 qcom,opp-acd-level = <0x882e5ffd>;
3843 opp-687000000 {
3844 opp-hz = /bits/ 64 <687000000>;
3845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3846 opp-peak-kBps = <8171875>;
3847 qcom,opp-acd-level = <0x882e5ffd>;
3850 opp-550000000 {
3851 opp-hz = /bits/ 64 <550000000>;
3852 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3853 opp-peak-kBps = <6074219>;
3854 qcom,opp-acd-level = <0xc0285ffd>;
3857 opp-390000000 {
3858 opp-hz = /bits/ 64 <390000000>;
3859 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3860 opp-peak-kBps = <3000000>;
3861 qcom,opp-acd-level = <0xc0285ffd>;
3864 opp-300000000 {
3865 opp-hz = /bits/ 64 <300000000>;
3866 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3867 opp-peak-kBps = <2136719>;
3868 qcom,opp-acd-level = <0xc02b5ffd>;
3874 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3878 reg-names = "gmu", "rscc", "gmu_pdc";
3882 interrupt-names = "hfi", "gmu";
3891 clock-names = "ahb",
3899 power-domains = <&gpucc GPU_CX_GDSC>,
3901 power-domain-names = "cx",
3908 operating-points-v2 = <&gmu_opp_table>;
3910 gmu_opp_table: opp-table {
3911 compatible = "operating-points-v2";
3913 opp-550000000 {
3914 opp-hz = /bits/ 64 <550000000>;
3915 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3918 opp-220000000 {
3919 opp-hz = /bits/ 64 <220000000>;
3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3925 gpucc: clock-controller@3d90000 {
3926 compatible = "qcom,x1e80100-gpucc";
3931 #clock-cells = <1>;
3932 #reset-cells = <1>;
3933 #power-domain-cells = <1>;
3937 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3938 "qcom,smmu-500", "arm,mmu-500";
3940 #iommu-cells = <2>;
3941 #global-interrupts = <1>;
3972 clock-names = "hlos",
3976 power-domains = <&gpucc GPU_CX_GDSC>;
3977 dma-coherent;
3981 compatible = "qcom,x1e80100-gem-noc";
3984 qcom,bcm-voters = <&apps_bcm_voter>;
3986 #interconnect-cells = <2>;
3990 compatible = "qcom,x1e80100-nsp-noc";
3993 qcom,bcm-voters = <&apps_bcm_voter>;
3995 #interconnect-cells = <2>;
3999 compatible = "qcom,x1e80100-adsp-pas";
4002 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4007 interrupt-names = "wdog",
4011 "stop-ack";
4014 clock-names = "xo";
4016 power-domains = <&rpmhpd RPMHPD_LCX>,
4018 power-domain-names = "lcx",
4024 memory-region = <&adspslpi_mem>,
4029 qcom,smem-states = <&smp2p_adsp_out 0>;
4030 qcom,smem-state-names = "stop";
4034 glink-edge {
4035 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4042 qcom,remote-pid = <2>;
4046 qcom,glink-channels = "fastrpcglink-apps-dsp";
4048 qcom,non-secure-domain;
4049 #address-cells = <1>;
4050 #size-cells = <0>;
4052 compute-cb@3 {
4053 compatible = "qcom,fastrpc-compute-cb";
4057 dma-coherent;
4060 compute-cb@4 {
4061 compatible = "qcom,fastrpc-compute-cb";
4065 dma-coherent;
4068 compute-cb@5 {
4069 compatible = "qcom,fastrpc-compute-cb";
4073 dma-coherent;
4076 compute-cb@6 {
4077 compatible = "qcom,fastrpc-compute-cb";
4081 dma-coherent;
4084 compute-cb@7 {
4085 compatible = "qcom,fastrpc-compute-cb";
4089 dma-coherent;
4095 qcom,glink-channels = "adsp_apps";
4098 #address-cells = <1>;
4099 #size-cells = <0>;
4104 #sound-dai-cells = <0>;
4105 qcom,protection-domain = "avs/audio",
4109 compatible = "qcom,q6apm-lpass-dais";
4110 #sound-dai-cells = <1>;
4114 compatible = "qcom,q6apm-dais";
4123 qcom,protection-domain = "avs/audio",
4126 q6prmcc: clock-controller {
4127 compatible = "qcom,q6prm-lpass-clocks";
4128 #clock-cells = <2>;
4136 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4142 clock-names = "mclk",
4147 #clock-cells = <0>;
4148 clock-output-names = "wsa2-mclk";
4149 #sound-dai-cells = <1>;
4150 sound-name-prefix = "WSA2";
4154 compatible = "qcom,soundwire-v2.0.0";
4157 clock-names = "iface";
4161 pinctrl-0 = <&wsa2_swr_active>;
4162 pinctrl-names = "default";
4164 reset-names = "swr_audio_cgcr";
4166 qcom,din-ports = <4>;
4167 qcom,dout-ports = <9>;
4169 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4170 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4171 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4172 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4173 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4174 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4175 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4176 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4177 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4179 #address-cells = <2>;
4180 #size-cells = <0>;
4181 #sound-dai-cells = <1>;
4186 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4192 clock-names = "mclk",
4197 #clock-cells = <0>;
4198 clock-output-names = "mclk";
4199 #sound-dai-cells = <1>;
4203 compatible = "qcom,soundwire-v2.0.0";
4206 clock-names = "iface";
4210 pinctrl-0 = <&rx_swr_active>;
4211 pinctrl-names = "default";
4214 reset-names = "swr_audio_cgcr";
4215 qcom,din-ports = <1>;
4216 qcom,dout-ports = <11>;
4218 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4219 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4220 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4221 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4222 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4223 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4224 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
4225 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4226 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4228 #address-cells = <2>;
4229 #size-cells = <0>;
4230 #sound-dai-cells = <1>;
4235 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4241 clock-names = "mclk",
4246 #clock-cells = <0>;
4247 clock-output-names = "mclk";
4248 #sound-dai-cells = <1>;
4252 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4258 clock-names = "mclk",
4263 #clock-cells = <0>;
4264 clock-output-names = "mclk";
4265 #sound-dai-cells = <1>;
4266 sound-name-prefix = "WSA";
4270 compatible = "qcom,soundwire-v2.0.0";
4273 clock-names = "iface";
4277 pinctrl-0 = <&wsa_swr_active>;
4278 pinctrl-names = "default";
4280 reset-names = "swr_audio_cgcr";
4282 qcom,din-ports = <4>;
4283 qcom,dout-ports = <9>;
4285 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
4286 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4287 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4288 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4289 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4290 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
4291 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
4292 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4293 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
4295 #address-cells = <2>;
4296 #size-cells = <0>;
4297 #sound-dai-cells = <1>;
4301 lpass_audiocc: clock-controller@6b6c000 {
4302 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
4304 #clock-cells = <1>;
4305 #reset-cells = <1>;
4309 compatible = "qcom,soundwire-v2.0.0";
4312 clock-names = "iface";
4315 interrupt-names = "core", "wakeup";
4318 reset-names = "swr_audio_cgcr";
4320 pinctrl-0 = <&tx_swr_active>;
4321 pinctrl-names = "default";
4323 qcom,din-ports = <4>;
4324 qcom,dout-ports = <1>;
4326 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4327 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4328 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4329 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4330 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4331 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4332 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4333 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4334 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4336 #address-cells = <2>;
4337 #size-cells = <0>;
4338 #sound-dai-cells = <1>;
4343 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4348 clock-names = "mclk",
4352 #clock-cells = <0>;
4353 clock-output-names = "fsgen";
4354 #sound-dai-cells = <1>;
4358 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
4364 clock-names = "core", "audio";
4366 gpio-controller;
4367 #gpio-cells = <2>;
4368 gpio-ranges = <&lpass_tlmm 0 0 23>;
4370 tx_swr_active: tx-swr-active-state {
4371 clk-pins {
4374 drive-strength = <2>;
4375 slew-rate = <1>;
4376 bias-disable;
4379 data-pins {
4382 drive-strength = <2>;
4383 slew-rate = <1>;
4384 bias-bus-hold;
4388 rx_swr_active: rx-swr-active-state {
4389 clk-pins {
4392 drive-strength = <2>;
4393 slew-rate = <1>;
4394 bias-disable;
4397 data-pins {
4400 drive-strength = <2>;
4401 slew-rate = <1>;
4402 bias-bus-hold;
4406 dmic01_default: dmic01-default-state {
4407 clk-pins {
4410 drive-strength = <8>;
4411 output-high;
4414 data-pins {
4417 drive-strength = <8>;
4418 input-enable;
4422 dmic23_default: dmic23-default-state {
4423 clk-pins {
4426 drive-strength = <8>;
4427 output-high;
4430 data-pins {
4433 drive-strength = <8>;
4434 input-enable;
4438 wsa_swr_active: wsa-swr-active-state {
4439 clk-pins {
4442 drive-strength = <2>;
4443 slew-rate = <1>;
4444 bias-disable;
4447 data-pins {
4450 drive-strength = <2>;
4451 slew-rate = <1>;
4452 bias-bus-hold;
4456 wsa2_swr_active: wsa2-swr-active-state {
4457 clk-pins {
4460 drive-strength = <2>;
4461 slew-rate = <1>;
4462 bias-disable;
4465 data-pins {
4468 drive-strength = <2>;
4469 slew-rate = <1>;
4470 bias-bus-hold;
4475 lpasscc: clock-controller@6ea0000 {
4476 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
4478 #clock-cells = <1>;
4479 #reset-cells = <1>;
4483 compatible = "qcom,x1e80100-lpass-ag-noc";
4486 qcom,bcm-voters = <&apps_bcm_voter>;
4488 #interconnect-cells = <2>;
4492 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
4495 qcom,bcm-voters = <&apps_bcm_voter>;
4497 #interconnect-cells = <2>;
4501 compatible = "qcom,x1e80100-lpass-lpicx-noc";
4504 qcom,bcm-voters = <&apps_bcm_voter>;
4506 #interconnect-cells = <2>;
4510 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4515 interrupt-names = "hc_irq", "pwr_irq";
4520 clock-names = "iface", "core", "xo";
4522 qcom,dll-config = <0x0007642c>;
4523 qcom,ddr-config = <0x80040868>;
4524 power-domains = <&rpmhpd RPMHPD_CX>;
4525 operating-points-v2 = <&sdhc2_opp_table>;
4531 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4532 bus-width = <4>;
4533 dma-coherent;
4537 sdhc2_opp_table: opp-table {
4538 compatible = "operating-points-v2";
4540 opp-19200000 {
4541 opp-hz = /bits/ 64 <19200000>;
4542 required-opps = <&rpmhpd_opp_min_svs>;
4545 opp-50000000 {
4546 opp-hz = /bits/ 64 <50000000>;
4547 required-opps = <&rpmhpd_opp_low_svs>;
4550 opp-100000000 {
4551 opp-hz = /bits/ 64 <100000000>;
4552 required-opps = <&rpmhpd_opp_svs>;
4555 opp-202000000 {
4556 opp-hz = /bits/ 64 <202000000>;
4557 required-opps = <&rpmhpd_opp_svs_l1>;
4563 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4568 interrupt-names = "hc_irq", "pwr_irq";
4573 clock-names = "iface", "core", "xo";
4575 qcom,dll-config = <0x0007642c>;
4576 qcom,ddr-config = <0x80040868>;
4577 power-domains = <&rpmhpd RPMHPD_CX>;
4578 operating-points-v2 = <&sdhc4_opp_table>;
4584 interconnect-names = "sdhc-ddr", "cpu-sdhc";
4585 bus-width = <4>;
4586 dma-coherent;
4590 sdhc4_opp_table: opp-table {
4591 compatible = "operating-points-v2";
4593 opp-19200000 {
4594 opp-hz = /bits/ 64 <19200000>;
4595 required-opps = <&rpmhpd_opp_min_svs>;
4598 opp-50000000 {
4599 opp-hz = /bits/ 64 <50000000>;
4600 required-opps = <&rpmhpd_opp_low_svs>;
4603 opp-100000000 {
4604 opp-hz = /bits/ 64 <100000000>;
4605 required-opps = <&rpmhpd_opp_svs>;
4608 opp-202000000 {
4609 opp-hz = /bits/ 64 <202000000>;
4610 required-opps = <&rpmhpd_opp_svs_l1>;
4616 compatible = "qcom,x1e80100-snps-eusb2-phy",
4617 "qcom,sm8550-snps-eusb2-phy";
4619 #phy-cells = <0>;
4622 clock-names = "ref";
4630 compatible = "qcom,x1e80100-snps-eusb2-phy",
4631 "qcom,sm8550-snps-eusb2-phy";
4633 #phy-cells = <0>;
4636 clock-names = "ref";
4644 compatible = "qcom,x1e80100-snps-eusb2-phy",
4645 "qcom,sm8550-snps-eusb2-phy";
4647 #phy-cells = <0>;
4650 clock-names = "ref";
4658 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4665 clock-names = "aux",
4672 reset-names = "phy",
4675 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
4677 #clock-cells = <0>;
4678 clock-output-names = "usb_mp_phy0_pipe_clk";
4680 #phy-cells = <0>;
4686 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4693 clock-names = "aux",
4700 reset-names = "phy",
4703 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
4705 #clock-cells = <0>;
4706 clock-output-names = "usb_mp_phy1_pipe_clk";
4708 #phy-cells = <0>;
4714 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4726 clock-names = "cfg_noc",
4736 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4738 assigned-clock-rates = <19200000>,
4741 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4745 interrupt-names = "pwr_event",
4750 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4751 required-opps = <&rpmhpd_opp_nom>;
4759 interconnect-names = "usb-ddr",
4760 "apps-usb";
4762 wakeup-source;
4764 #address-cells = <2>;
4765 #size-cells = <2>;
4780 phy-names = "usb2-phy",
4781 "usb3-phy";
4786 snps,dis-u1-entry-quirk;
4787 snps,dis-u2-entry-quirk;
4789 dma-coherent;
4792 #address-cells = <1>;
4793 #size-cells = <0>;
4806 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4814 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4816 #address-cells = <2>;
4817 #size-cells = <2>;
4829 clock-names = "cfg_noc",
4839 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4841 assigned-clock-rates = <19200000>, <200000000>;
4843 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
4846 interrupt-names = "pwr_event",
4850 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4851 required-opps = <&rpmhpd_opp_nom>;
4859 interconnect-names = "usb-ddr",
4860 "apps-usb";
4862 wakeup-source;
4872 phy-names = "usb2-phy";
4873 maximum-speed = "high-speed";
4874 snps,dis-u1-entry-quirk;
4875 snps,dis-u2-entry-quirk;
4877 dma-coherent;
4880 #address-cells = <1>;
4881 #size-cells = <0>;
4894 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4906 clock-names = "cfg_noc",
4916 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4918 assigned-clock-rates = <19200000>,
4921 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4931 interrupt-names = "pwr_event_1", "pwr_event_2",
4937 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4938 required-opps = <&rpmhpd_opp_nom>;
4946 interconnect-names = "usb-ddr",
4947 "apps-usb";
4949 wakeup-source;
4951 #address-cells = <2>;
4952 #size-cells = <2>;
4967 phy-names = "usb2-0", "usb3-0",
4968 "usb2-1", "usb3-1";
4974 snps,dis-u1-entry-quirk;
4975 snps,dis-u2-entry-quirk;
4977 dma-coherent;
4982 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4994 clock-names = "cfg_noc",
5004 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5006 assigned-clock-rates = <19200000>,
5009 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
5013 interrupt-names = "pwr_event",
5018 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
5019 required-opps = <&rpmhpd_opp_nom>;
5023 wakeup-source;
5025 #address-cells = <2>;
5026 #size-cells = <2>;
5041 phy-names = "usb2-phy",
5042 "usb3-phy";
5047 snps,dis-u1-entry-quirk;
5048 snps,dis-u2-entry-quirk;
5050 dma-coherent;
5053 #address-cells = <1>;
5054 #size-cells = <0>;
5067 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
5075 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5087 clock-names = "cfg_noc",
5097 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5099 assigned-clock-rates = <19200000>,
5102 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
5106 interrupt-names = "pwr_event",
5111 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
5112 required-opps = <&rpmhpd_opp_nom>;
5120 interconnect-names = "usb-ddr",
5121 "apps-usb";
5123 wakeup-source;
5125 #address-cells = <2>;
5126 #size-cells = <2>;
5141 phy-names = "usb2-phy",
5142 "usb3-phy";
5147 snps,dis-u1-entry-quirk;
5148 snps,dis-u2-entry-quirk;
5150 dma-coherent;
5153 #address-cells = <1>;
5154 #size-cells = <0>;
5167 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
5174 mdss: display-subsystem@ae00000 {
5175 compatible = "qcom,x1e80100-mdss";
5177 reg-names = "mdss";
5193 interconnect-names = "mdp0-mem",
5194 "mdp1-mem",
5195 "cpu-cfg";
5197 power-domains = <&dispcc MDSS_GDSC>;
5201 interrupt-controller;
5202 #interrupt-cells = <1>;
5204 #address-cells = <2>;
5205 #size-cells = <2>;
5210 mdss_mdp: display-controller@ae01000 {
5211 compatible = "qcom,x1e80100-dpu";
5214 reg-names = "mdp",
5217 interrupts-extended = <&mdss 0>;
5224 clock-names = "nrt_bus",
5230 operating-points-v2 = <&mdp_opp_table>;
5232 power-domains = <&rpmhpd RPMHPD_MMCX>;
5235 #address-cells = <1>;
5236 #size-cells = <0>;
5242 remote-endpoint = <&mdss_dp0_in>;
5250 remote-endpoint = <&mdss_dp1_in>;
5258 remote-endpoint = <&mdss_dp3_in>;
5266 remote-endpoint = <&mdss_dp2_in>;
5271 mdp_opp_table: opp-table {
5272 compatible = "operating-points-v2";
5274 opp-200000000 {
5275 opp-hz = /bits/ 64 <200000000>;
5276 required-opps = <&rpmhpd_opp_low_svs>;
5279 opp-325000000 {
5280 opp-hz = /bits/ 64 <325000000>;
5281 required-opps = <&rpmhpd_opp_svs>;
5284 opp-375000000 {
5285 opp-hz = /bits/ 64 <375000000>;
5286 required-opps = <&rpmhpd_opp_svs_l1>;
5289 opp-514000000 {
5290 opp-hz = /bits/ 64 <514000000>;
5291 required-opps = <&rpmhpd_opp_nom>;
5294 opp-575000000 {
5295 opp-hz = /bits/ 64 <575000000>;
5296 required-opps = <&rpmhpd_opp_nom_l1>;
5301 mdss_dp0: displayport-controller@ae90000 {
5302 compatible = "qcom,x1e80100-dp";
5309 interrupts-extended = <&mdss 12>;
5316 clock-names = "core_iface",
5322 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5324 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5327 operating-points-v2 = <&mdss_dp0_opp_table>;
5329 power-domains = <&rpmhpd RPMHPD_MMCX>;
5332 phy-names = "dp";
5334 #sound-dai-cells = <0>;
5339 #address-cells = <1>;
5340 #size-cells = <0>;
5346 remote-endpoint = <&mdss_intf0_out>;
5354 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
5359 mdss_dp0_opp_table: opp-table {
5360 compatible = "operating-points-v2";
5362 opp-160000000 {
5363 opp-hz = /bits/ 64 <160000000>;
5364 required-opps = <&rpmhpd_opp_low_svs>;
5367 opp-270000000 {
5368 opp-hz = /bits/ 64 <270000000>;
5369 required-opps = <&rpmhpd_opp_svs>;
5372 opp-540000000 {
5373 opp-hz = /bits/ 64 <540000000>;
5374 required-opps = <&rpmhpd_opp_svs_l1>;
5377 opp-810000000 {
5378 opp-hz = /bits/ 64 <810000000>;
5379 required-opps = <&rpmhpd_opp_nom>;
5384 mdss_dp1: displayport-controller@ae98000 {
5385 compatible = "qcom,x1e80100-dp";
5392 interrupts-extended = <&mdss 13>;
5399 clock-names = "core_iface",
5405 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5407 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5410 operating-points-v2 = <&mdss_dp1_opp_table>;
5412 power-domains = <&rpmhpd RPMHPD_MMCX>;
5415 phy-names = "dp";
5417 #sound-dai-cells = <0>;
5422 #address-cells = <1>;
5423 #size-cells = <0>;
5429 remote-endpoint = <&mdss_intf4_out>;
5437 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
5442 mdss_dp1_opp_table: opp-table {
5443 compatible = "operating-points-v2";
5445 opp-160000000 {
5446 opp-hz = /bits/ 64 <160000000>;
5447 required-opps = <&rpmhpd_opp_low_svs>;
5450 opp-270000000 {
5451 opp-hz = /bits/ 64 <270000000>;
5452 required-opps = <&rpmhpd_opp_svs>;
5455 opp-540000000 {
5456 opp-hz = /bits/ 64 <540000000>;
5457 required-opps = <&rpmhpd_opp_svs_l1>;
5460 opp-810000000 {
5461 opp-hz = /bits/ 64 <810000000>;
5462 required-opps = <&rpmhpd_opp_nom>;
5467 mdss_dp2: displayport-controller@ae9a000 {
5468 compatible = "qcom,x1e80100-dp";
5475 interrupts-extended = <&mdss 14>;
5482 clock-names = "core_iface",
5488 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5490 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5493 operating-points-v2 = <&mdss_dp2_opp_table>;
5495 power-domains = <&rpmhpd RPMHPD_MMCX>;
5498 phy-names = "dp";
5500 #sound-dai-cells = <0>;
5505 #address-cells = <1>;
5506 #size-cells = <0>;
5511 remote-endpoint = <&mdss_intf6_out>;
5519 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
5524 mdss_dp2_opp_table: opp-table {
5525 compatible = "operating-points-v2";
5527 opp-160000000 {
5528 opp-hz = /bits/ 64 <160000000>;
5529 required-opps = <&rpmhpd_opp_low_svs>;
5532 opp-270000000 {
5533 opp-hz = /bits/ 64 <270000000>;
5534 required-opps = <&rpmhpd_opp_svs>;
5537 opp-540000000 {
5538 opp-hz = /bits/ 64 <540000000>;
5539 required-opps = <&rpmhpd_opp_svs_l1>;
5542 opp-810000000 {
5543 opp-hz = /bits/ 64 <810000000>;
5544 required-opps = <&rpmhpd_opp_nom>;
5549 mdss_dp3: displayport-controller@aea0000 {
5550 compatible = "qcom,x1e80100-dp";
5557 interrupts-extended = <&mdss 15>;
5564 clock-names = "core_iface",
5570 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5572 assigned-clock-parents = <&mdss_dp3_phy 0>,
5575 operating-points-v2 = <&mdss_dp3_opp_table>;
5577 power-domains = <&rpmhpd RPMHPD_MMCX>;
5580 phy-names = "dp";
5582 #sound-dai-cells = <0>;
5587 #address-cells = <1>;
5588 #size-cells = <0>;
5594 remote-endpoint = <&mdss_intf5_out>;
5603 mdss_dp3_opp_table: opp-table {
5604 compatible = "operating-points-v2";
5606 opp-160000000 {
5607 opp-hz = /bits/ 64 <160000000>;
5608 required-opps = <&rpmhpd_opp_low_svs>;
5611 opp-270000000 {
5612 opp-hz = /bits/ 64 <270000000>;
5613 required-opps = <&rpmhpd_opp_svs>;
5616 opp-540000000 {
5617 opp-hz = /bits/ 64 <540000000>;
5618 required-opps = <&rpmhpd_opp_svs_l1>;
5621 opp-810000000 {
5622 opp-hz = /bits/ 64 <810000000>;
5623 required-opps = <&rpmhpd_opp_nom>;
5631 compatible = "qcom,x1e80100-dp-phy";
5639 clock-names = "aux",
5642 power-domains = <&rpmhpd RPMHPD_MX>;
5644 #clock-cells = <1>;
5645 #phy-cells = <0>;
5651 compatible = "qcom,x1e80100-dp-phy";
5659 clock-names = "aux",
5662 power-domains = <&rpmhpd RPMHPD_MX>;
5664 #clock-cells = <1>;
5665 #phy-cells = <0>;
5670 dispcc: clock-controller@af00000 {
5671 compatible = "qcom,x1e80100-dispcc";
5689 power-domains = <&rpmhpd RPMHPD_MMCX>;
5690 required-opps = <&rpmhpd_opp_low_svs>;
5691 #clock-cells = <1>;
5692 #reset-cells = <1>;
5693 #power-domain-cells = <1>;
5696 pdc: interrupt-controller@b220000 {
5697 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
5700 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5703 #interrupt-cells = <2>;
5704 interrupt-parent = <&intc>;
5705 interrupt-controller;
5708 aoss_qmp: power-management@c300000 {
5709 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
5711 interrupt-parent = <&ipcc>;
5712 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5716 #clock-cells = <0>;
5720 compatible = "qcom,rpmh-stats";
5725 compatible = "qcom,x1e80100-spmi-pmic-arb";
5729 reg-names = "core", "chnls", "obsrvr";
5734 #address-cells = <2>;
5735 #size-cells = <2>;
5741 reg-names = "cnfg", "intr";
5743 interrupt-names = "periph_irq";
5744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5745 interrupt-controller;
5746 #interrupt-cells = <4>;
5748 #address-cells = <2>;
5749 #size-cells = <0>;
5755 reg-names = "cnfg", "intr";
5757 interrupt-names = "periph_irq";
5758 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5759 interrupt-controller;
5760 #interrupt-cells = <4>;
5762 #address-cells = <2>;
5763 #size-cells = <0>;
5768 compatible = "qcom,x1e80100-tlmm";
5773 gpio-controller;
5774 #gpio-cells = <2>;
5776 interrupt-controller;
5777 #interrupt-cells = <2>;
5779 gpio-ranges = <&tlmm 0 0 239>;
5780 wakeup-parent = <&pdc>;
5782 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5786 drive-strength = <2>;
5787 bias-pull-up = <2200>;
5790 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5794 drive-strength = <2>;
5795 bias-pull-up = <2200>;
5798 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5802 drive-strength = <2>;
5803 bias-pull-up = <2200>;
5806 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5810 drive-strength = <2>;
5811 bias-pull-up = <2200>;
5814 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5818 drive-strength = <2>;
5819 bias-pull-up = <2200>;
5822 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5826 drive-strength = <2>;
5827 bias-pull-up = <2200>;
5830 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5834 drive-strength = <2>;
5835 bias-pull-up = <2200>;
5838 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5842 drive-strength = <2>;
5843 bias-pull-up = <2200>;
5846 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5850 drive-strength = <2>;
5851 bias-pull-up = <2200>;
5854 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5858 drive-strength = <2>;
5859 bias-pull-up = <2200>;
5862 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5866 drive-strength = <2>;
5867 bias-pull-up = <2200>;
5870 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5874 drive-strength = <2>;
5875 bias-pull-up = <2200>;
5878 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5882 drive-strength = <2>;
5883 bias-pull-up = <2200>;
5886 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5890 drive-strength = <2>;
5891 bias-pull-up = <2200>;
5894 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5898 drive-strength = <2>;
5899 bias-pull-up = <2200>;
5902 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5906 drive-strength = <2>;
5907 bias-pull-up = <2200>;
5910 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5914 drive-strength = <2>;
5915 bias-pull-up = <2200>;
5918 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5922 drive-strength = <2>;
5923 bias-pull-up = <2200>;
5926 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5930 drive-strength = <2>;
5931 bias-pull-up = <2200>;
5934 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5938 drive-strength = <2>;
5939 bias-pull-up = <2200>;
5942 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5946 drive-strength = <2>;
5947 bias-pull-up = <2200>;
5950 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5954 drive-strength = <2>;
5955 bias-pull-up = <2200>;
5958 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5962 drive-strength = <2>;
5963 bias-pull-up = <2200>;
5966 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5970 drive-strength = <2>;
5971 bias-pull-up = <2200>;
5974 qup_spi0_cs: qup-spi0-cs-state {
5977 drive-strength = <6>;
5978 bias-disable;
5981 qup_spi0_data_clk: qup-spi0-data-clk-state {
5985 drive-strength = <6>;
5986 bias-disable;
5989 qup_spi1_cs: qup-spi1-cs-state {
5992 drive-strength = <6>;
5993 bias-disable;
5996 qup_spi1_data_clk: qup-spi1-data-clk-state {
6000 drive-strength = <6>;
6001 bias-disable;
6004 qup_spi2_cs: qup-spi2-cs-state {
6007 drive-strength = <6>;
6008 bias-disable;
6011 qup_spi2_data_clk: qup-spi2-data-clk-state {
6015 drive-strength = <6>;
6016 bias-disable;
6019 qup_spi3_cs: qup-spi3-cs-state {
6022 drive-strength = <6>;
6023 bias-disable;
6026 qup_spi3_data_clk: qup-spi3-data-clk-state {
6030 drive-strength = <6>;
6031 bias-disable;
6034 qup_spi4_cs: qup-spi4-cs-state {
6037 drive-strength = <6>;
6038 bias-disable;
6041 qup_spi4_data_clk: qup-spi4-data-clk-state {
6045 drive-strength = <6>;
6046 bias-disable;
6049 qup_spi5_cs: qup-spi5-cs-state {
6052 drive-strength = <6>;
6053 bias-disable;
6056 qup_spi5_data_clk: qup-spi5-data-clk-state {
6060 drive-strength = <6>;
6061 bias-disable;
6064 qup_spi6_cs: qup-spi6-cs-state {
6067 drive-strength = <6>;
6068 bias-disable;
6071 qup_spi6_data_clk: qup-spi6-data-clk-state {
6075 drive-strength = <6>;
6076 bias-disable;
6079 qup_spi7_cs: qup-spi7-cs-state {
6082 drive-strength = <6>;
6083 bias-disable;
6086 qup_spi7_data_clk: qup-spi7-data-clk-state {
6090 drive-strength = <6>;
6091 bias-disable;
6094 qup_spi8_cs: qup-spi8-cs-state {
6097 drive-strength = <6>;
6098 bias-disable;
6101 qup_spi8_data_clk: qup-spi8-data-clk-state {
6105 drive-strength = <6>;
6106 bias-disable;
6109 qup_spi9_cs: qup-spi9-cs-state {
6112 drive-strength = <6>;
6113 bias-disable;
6116 qup_spi9_data_clk: qup-spi9-data-clk-state {
6120 drive-strength = <6>;
6121 bias-disable;
6124 qup_spi10_cs: qup-spi10-cs-state {
6127 drive-strength = <6>;
6128 bias-disable;
6131 qup_spi10_data_clk: qup-spi10-data-clk-state {
6135 drive-strength = <6>;
6136 bias-disable;
6139 qup_spi11_cs: qup-spi11-cs-state {
6142 drive-strength = <6>;
6143 bias-disable;
6146 qup_spi11_data_clk: qup-spi11-data-clk-state {
6150 drive-strength = <6>;
6151 bias-disable;
6154 qup_spi12_cs: qup-spi12-cs-state {
6157 drive-strength = <6>;
6158 bias-disable;
6161 qup_spi12_data_clk: qup-spi12-data-clk-state {
6165 drive-strength = <6>;
6166 bias-disable;
6169 qup_spi13_cs: qup-spi13-cs-state {
6172 drive-strength = <6>;
6173 bias-disable;
6176 qup_spi13_data_clk: qup-spi13-data-clk-state {
6180 drive-strength = <6>;
6181 bias-disable;
6184 qup_spi14_cs: qup-spi14-cs-state {
6187 drive-strength = <6>;
6188 bias-disable;
6191 qup_spi14_data_clk: qup-spi14-data-clk-state {
6195 drive-strength = <6>;
6196 bias-disable;
6199 qup_spi15_cs: qup-spi15-cs-state {
6202 drive-strength = <6>;
6203 bias-disable;
6206 qup_spi15_data_clk: qup-spi15-data-clk-state {
6210 drive-strength = <6>;
6211 bias-disable;
6214 qup_spi16_cs: qup-spi16-cs-state {
6217 drive-strength = <6>;
6218 bias-disable;
6221 qup_spi16_data_clk: qup-spi16-data-clk-state {
6225 drive-strength = <6>;
6226 bias-disable;
6229 qup_spi17_cs: qup-spi17-cs-state {
6232 drive-strength = <6>;
6233 bias-disable;
6236 qup_spi17_data_clk: qup-spi17-data-clk-state {
6240 drive-strength = <6>;
6241 bias-disable;
6244 qup_spi18_cs: qup-spi18-cs-state {
6247 drive-strength = <6>;
6248 bias-disable;
6251 qup_spi18_data_clk: qup-spi18-data-clk-state {
6255 drive-strength = <6>;
6256 bias-disable;
6259 qup_spi19_cs: qup-spi19-cs-state {
6262 drive-strength = <6>;
6263 bias-disable;
6266 qup_spi19_data_clk: qup-spi19-data-clk-state {
6270 drive-strength = <6>;
6271 bias-disable;
6274 qup_spi20_cs: qup-spi20-cs-state {
6277 drive-strength = <6>;
6278 bias-disable;
6281 qup_spi20_data_clk: qup-spi20-data-clk-state {
6285 drive-strength = <6>;
6286 bias-disable;
6289 qup_spi21_cs: qup-spi21-cs-state {
6292 drive-strength = <6>;
6293 bias-disable;
6296 qup_spi21_data_clk: qup-spi21-data-clk-state {
6300 drive-strength = <6>;
6301 bias-disable;
6304 qup_spi22_cs: qup-spi22-cs-state {
6307 drive-strength = <6>;
6308 bias-disable;
6311 qup_spi22_data_clk: qup-spi22-data-clk-state {
6315 drive-strength = <6>;
6316 bias-disable;
6319 qup_spi23_cs: qup-spi23-cs-state {
6322 drive-strength = <6>;
6323 bias-disable;
6326 qup_spi23_data_clk: qup-spi23-data-clk-state {
6330 drive-strength = <6>;
6331 bias-disable;
6334 qup_uart2_default: qup-uart2-default-state {
6335 cts-pins {
6338 drive-strength = <2>;
6339 bias-disable;
6342 rts-pins {
6345 drive-strength = <2>;
6346 bias-disable;
6349 tx-pins {
6352 drive-strength = <2>;
6353 bias-disable;
6356 rx-pins {
6359 drive-strength = <2>;
6360 bias-disable;
6364 qup_uart14_default: qup-uart14-default-state {
6365 cts-pins {
6368 bias-bus-hold;
6371 rts-pins {
6374 drive-strength = <2>;
6375 bias-disable;
6378 tx-pins {
6381 drive-strength = <2>;
6382 bias-disable;
6385 rx-pins {
6388 bias-pull-up;
6392 qup_uart21_default: qup-uart21-default-state {
6393 tx-pins {
6396 drive-strength = <2>;
6397 bias-disable;
6400 rx-pins {
6403 drive-strength = <2>;
6404 bias-disable;
6408 sdc2_default: sdc2-default-state {
6409 clk-pins {
6411 drive-strength = <16>;
6412 bias-disable;
6415 cmd-pins {
6417 drive-strength = <10>;
6418 bias-pull-up;
6421 data-pins {
6423 drive-strength = <10>;
6424 bias-pull-up;
6428 sdc2_sleep: sdc2-sleep-state {
6429 clk-pins {
6431 drive-strength = <2>;
6432 bias-disable;
6435 cmd-pins {
6437 drive-strength = <2>;
6438 bias-pull-up;
6441 data-pins {
6443 drive-strength = <2>;
6444 bias-pull-up;
6450 compatible = "arm,coresight-stm", "arm,primecell";
6453 reg-names = "stm-base",
6454 "stm-stimulus-base";
6457 clock-names = "apb_pclk";
6459 out-ports {
6462 remote-endpoint = <&funnel0_in7>;
6469 compatible = "qcom,coresight-tpdm", "arm,primecell";
6473 clock-names = "apb_pclk";
6475 qcom,cmb-element-bits = <32>;
6476 qcom,cmb-msrs-num = <32>;
6479 out-ports {
6482 remote-endpoint = <&qdss_tpda_in0>;
6489 compatible = "qcom,coresight-tpda", "arm,primecell";
6493 clock-names = "apb_pclk";
6495 in-ports {
6496 #address-cells = <1>;
6497 #size-cells = <0>;
6503 remote-endpoint = <&dcc_tpdm_out>;
6511 remote-endpoint = <&qdss_tpdm_out>;
6516 out-ports {
6519 remote-endpoint = <&funnel0_in6>;
6526 compatible = "qcom,coresight-tpdm", "arm,primecell";
6530 clock-names = "apb_pclk";
6532 qcom,cmb-element-bits = <32>;
6533 qcom,cmb-msrs-num = <32>;
6535 out-ports {
6538 remote-endpoint = <&qdss_tpda_in1>;
6545 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6549 clock-names = "apb_pclk";
6551 in-ports {
6552 #address-cells = <1>;
6553 #size-cells = <0>;
6559 remote-endpoint = <&qdss_tpda_out>;
6567 remote-endpoint = <&stm_out>;
6572 out-ports {
6575 remote-endpoint = <&qdss_funnel_in0>;
6582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6586 clock-names = "apb_pclk";
6588 in-ports {
6589 #address-cells = <1>;
6590 #size-cells = <0>;
6596 remote-endpoint = <&tmess_funnel_out>;
6604 remote-endpoint = <&dlst_funnel_out>;
6612 remote-endpoint = <&dlct1_funnel_out>;
6617 out-ports {
6620 remote-endpoint = <&qdss_funnel_in1>;
6627 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6631 clock-names = "apb_pclk";
6633 in-ports {
6634 #address-cells = <1>;
6635 #size-cells = <0>;
6641 remote-endpoint = <&funnel0_out>;
6649 remote-endpoint = <&funnel1_out>;
6654 out-ports {
6657 remote-endpoint = <&aoss_funnel_in7>;
6664 compatible = "qcom,coresight-tpdm", "arm,primecell";
6668 clock-names = "apb_pclk";
6670 qcom,cmb-element-bits = <64>;
6671 qcom,cmb-msrs-num = <32>;
6673 out-ports {
6676 remote-endpoint = <&dlct2_tpda_in15>;
6683 compatible = "qcom,coresight-tpdm", "arm,primecell";
6687 clock-names = "apb_pclk";
6689 qcom,dsb-element-bits = <32>;
6690 qcom,dsb-msrs-num = <32>;
6692 out-ports {
6695 remote-endpoint = <&dlct1_tpda_in21>;
6702 compatible = "qcom,coresight-tpdm", "arm,primecell";
6706 clock-names = "apb_pclk";
6708 qcom,cmb-element-bits = <32>;
6709 qcom,cmb-msrs-num = <32>;
6711 out-ports {
6714 remote-endpoint = <&dlct1_tpda_in19>;
6721 compatible = "qcom,coresight-tpdm", "arm,primecell";
6725 clock-names = "apb_pclk";
6727 qcom,dsb-element-bits = <32>;
6728 qcom,dsb-msrs-num = <32>;
6730 out-ports {
6733 remote-endpoint = <&lpass_cx_funnel_in0>;
6740 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6744 clock-names = "apb_pclk";
6746 in-ports {
6749 remote-endpoint = <&lpass_cx_tpdm_out>;
6754 out-ports {
6757 remote-endpoint = <&dlct1_tpda_in4>;
6764 compatible = "arm,coresight-cti", "arm,primecell";
6768 clock-names = "apb_pclk";
6772 compatible = "qcom,coresight-tpdm", "arm,primecell";
6776 clock-names = "apb_pclk";
6778 qcom,dsb-element-bits = <32>;
6779 qcom,dsb-msrs-num = <32>;
6782 out-ports {
6785 remote-endpoint = <&dlct1_tpda_in20>;
6792 compatible = "qcom,coresight-tpdm", "arm,primecell";
6796 clock-names = "apb_pclk";
6798 qcom,dsb-element-bits = <32>;
6799 qcom,dsb-msrs-num = <32>;
6802 out-ports {
6805 remote-endpoint = <&dlst_tpda_in8>;
6812 compatible = "qcom,coresight-tpdm", "arm,primecell";
6816 clock-names = "apb_pclk";
6818 qcom,cmb-element-bits = <64>;
6819 qcom,cmb-msrs-num = <32>;
6821 out-ports {
6824 remote-endpoint = <&dlst_tpda_in9>;
6831 compatible = "qcom,coresight-tpda", "arm,primecell";
6835 clock-names = "apb_pclk";
6837 in-ports {
6838 #address-cells = <1>;
6839 #size-cells = <0>;
6845 remote-endpoint = <&dlst_tpdm0_out>;
6853 remote-endpoint = <&dlst_tpdm1_out>;
6858 out-ports {
6861 remote-endpoint = <&dlst_funnel_in0>;
6868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6872 clock-names = "apb_pclk";
6874 in-ports {
6877 remote-endpoint = <&dlst_tpda_out>;
6882 out-ports {
6885 remote-endpoint = <&funnel1_in5>;
6892 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6896 clock-names = "apb_pclk";
6898 in-ports {
6899 #address-cells = <1>;
6900 #size-cells = <0>;
6906 remote-endpoint = <&ddr_lpi_funnel_out>;
6914 remote-endpoint = <&aoss_tpda_out>;
6922 remote-endpoint = <&qdss_funnel_out>;
6927 out-ports {
6930 remote-endpoint = <&etf0_in>;
6937 compatible = "arm,coresight-tmc", "arm,primecell";
6941 clock-names = "apb_pclk";
6943 in-ports {
6946 remote-endpoint = <&aoss_funnel_out>;
6951 out-ports {
6954 remote-endpoint = <&swao_rep_in>;
6961 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
6965 clock-names = "apb_pclk";
6967 in-ports {
6970 remote-endpoint = <&etf0_out>;
6975 out-ports {
6978 remote-endpoint = <&eud_in>;
6985 compatible = "qcom,coresight-tpda", "arm,primecell";
6989 clock-names = "apb_pclk";
6991 in-ports {
6992 #address-cells = <1>;
6993 #size-cells = <0>;
6999 remote-endpoint = <&aoss_tpdm0_out>;
7007 remote-endpoint = <&aoss_tpdm1_out>;
7015 remote-endpoint = <&aoss_tpdm2_out>;
7023 remote-endpoint = <&aoss_tpdm3_out>;
7031 remote-endpoint = <&aoss_tpdm4_out>;
7036 out-ports {
7039 remote-endpoint = <&aoss_funnel_in6>;
7046 compatible = "qcom,coresight-tpdm", "arm,primecell";
7050 clock-names = "apb_pclk";
7052 qcom,cmb-element-bits = <64>;
7053 qcom,cmb-msrs-num = <32>;
7055 out-ports {
7058 remote-endpoint = <&aoss_tpda_in0>;
7065 compatible = "qcom,coresight-tpdm", "arm,primecell";
7069 clock-names = "apb_pclk";
7071 qcom,cmb-element-bits = <64>;
7072 qcom,cmb-msrs-num = <32>;
7074 out-ports {
7077 remote-endpoint = <&aoss_tpda_in1>;
7084 compatible = "qcom,coresight-tpdm", "arm,primecell";
7088 clock-names = "apb_pclk";
7090 qcom,cmb-element-bits = <64>;
7091 qcom,cmb-msrs-num = <32>;
7093 out-ports {
7096 remote-endpoint = <&aoss_tpda_in2>;
7103 compatible = "qcom,coresight-tpdm", "arm,primecell";
7107 clock-names = "apb_pclk";
7109 qcom,cmb-element-bits = <64>;
7110 qcom,cmb-msrs-num = <32>;
7112 out-ports {
7115 remote-endpoint = <&aoss_tpda_in3>;
7122 compatible = "qcom,coresight-tpdm", "arm,primecell";
7126 clock-names = "apb_pclk";
7128 qcom,dsb-element-bits = <32>;
7129 qcom,dsb-msrs-num = <32>;
7131 out-ports {
7134 remote-endpoint = <&aoss_tpda_in4>;
7141 compatible = "qcom,coresight-tpdm", "arm,primecell";
7145 clock-names = "apb_pclk";
7147 qcom,dsb-element-bits = <32>;
7148 qcom,dsb-msrs-num = <32>;
7151 out-ports {
7154 remote-endpoint = <&ddr_lpi_tpda_in>;
7161 compatible = "qcom,coresight-tpda", "arm,primecell";
7165 clock-names = "apb_pclk";
7168 in-ports {
7171 remote-endpoint = <&lpicc_tpdm_out>;
7176 out-ports {
7179 remote-endpoint = <&ddr_lpi_funnel_in0>;
7186 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7190 clock-names = "apb_pclk";
7193 in-ports {
7196 remote-endpoint = <&ddr_lpi_tpda_out>;
7201 out-ports {
7204 remote-endpoint = <&aoss_funnel_in3>;
7211 compatible = "qcom,coresight-tpdm", "arm,primecell";
7215 clock-names = "apb_pclk";
7217 qcom,dsb-element-bits = <32>;
7218 qcom,dsb-msrs-num = <32>;
7220 out-ports {
7223 remote-endpoint = <&mm_funnel_in4>;
7230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7234 clock-names = "apb_pclk";
7236 in-ports {
7237 #address-cells = <1>;
7238 #size-cells = <0>;
7244 remote-endpoint = <&mm_tpdm_out>;
7249 out-ports {
7252 remote-endpoint = <&dlct2_tpda_in4>;
7259 compatible = "qcom,coresight-tpdm", "arm,primecell";
7263 clock-names = "apb_pclk";
7265 qcom,dsb-element-bits = <32>;
7266 qcom,dsb-msrs-num = <32>;
7268 out-ports {
7271 remote-endpoint = <&dlct1_tpda_in26>;
7278 compatible = "qcom,coresight-tpdm", "arm,primecell";
7282 clock-names = "apb_pclk";
7284 qcom,cmb-element-bits = <64>;
7285 qcom,cmb-msrs-num = <32>;
7287 out-ports {
7290 remote-endpoint = <&dlct1_tpda_in27>;
7297 compatible = "qcom,coresight-tpda", "arm,primecell";
7301 clock-names = "apb_pclk";
7303 in-ports {
7304 #address-cells = <1>;
7305 #size-cells = <0>;
7311 remote-endpoint = <&lpass_cx_funnel_out>;
7319 remote-endpoint = <&prng_tpdm_out>;
7327 remote-endpoint = <&qm_tpdm_out>;
7335 remote-endpoint = <&gcc_tpdm_out>;
7343 remote-endpoint = <&dlct1_tpdm_out>;
7351 remote-endpoint = <&ipcc_tpdm_out>;
7356 out-ports {
7359 remote-endpoint = <&dlct1_funnel_in0>;
7366 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7370 clock-names = "apb_pclk";
7372 in-ports {
7373 #address-cells = <1>;
7374 #size-cells = <0>;
7380 remote-endpoint = <&dlct1_tpda_out>;
7388 remote-endpoint = <&dlct2_funnel_out>;
7396 remote-endpoint = <&ddr_funnel0_out>;
7401 out-ports {
7404 remote-endpoint = <&funnel1_in6>;
7411 compatible = "qcom,coresight-tpdm", "arm,primecell";
7415 clock-names = "apb_pclk";
7417 qcom,cmb-element-bits = <64>;
7418 qcom,cmb-msrs-num = <32>;
7420 out-ports {
7423 remote-endpoint = <&dlct2_tpda_in16>;
7430 compatible = "qcom,coresight-tpdm", "arm,primecell";
7434 clock-names = "apb_pclk";
7436 qcom,cmb-element-bits = <64>;
7437 qcom,cmb-msrs-num = <32>;
7439 out-ports {
7442 remote-endpoint = <&dlct2_tpda_in17>;
7449 compatible = "qcom,coresight-tpda", "arm,primecell";
7453 clock-names = "apb_pclk";
7455 in-ports {
7456 #address-cells = <1>;
7457 #size-cells = <0>;
7463 remote-endpoint = <&mm_funnel_out>;
7471 remote-endpoint = <&mxa_tpdm_out>;
7479 remote-endpoint = <&dlct2_tpdm0_out>;
7487 remote-endpoint = <&dlct2_tpdm1_out>;
7492 out-ports {
7495 remote-endpoint = <&dlct2_funnel_in0>;
7502 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7506 clock-names = "apb_pclk";
7508 in-ports {
7511 remote-endpoint = <&dlct2_tpda_out>;
7516 out-ports {
7519 remote-endpoint = <&dlct1_funnel_in4>;
7526 compatible = "qcom,coresight-tpdm", "arm,primecell";
7530 clock-names = "apb_pclk";
7532 qcom,cmb-element-bits = <64>;
7533 qcom,cmb-msrs-num = <32>;
7534 qcom,dsb-element-bits = <32>;
7535 qcom,dsb-msrs-num = <32>;
7538 out-ports {
7541 remote-endpoint = <&tmess_tpda_in2>;
7548 compatible = "qcom,coresight-tpda", "arm,primecell";
7552 clock-names = "apb_pclk";
7554 in-ports {
7555 #address-cells = <1>;
7556 #size-cells = <0>;
7562 remote-endpoint = <&tmess_tpdm1_out>;
7567 out-ports {
7570 remote-endpoint = <&tmess_funnel_in0>;
7577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7581 clock-names = "apb_pclk";
7583 in-ports {
7586 remote-endpoint = <&tmess_tpda_out>;
7591 out-ports {
7594 remote-endpoint = <&funnel1_in2>;
7601 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7605 clock-names = "apb_pclk";
7607 in-ports {
7608 #address-cells = <1>;
7609 #size-cells = <0>;
7615 remote-endpoint = <&ddr_funnel1_out>;
7620 out-ports {
7623 remote-endpoint = <&dlct1_funnel_in5>;
7630 compatible = "qcom,coresight-tpdm", "arm,primecell";
7634 clock-names = "apb_pclk";
7636 qcom,cmb-element-bits = <32>;
7637 qcom,cmb-msrs-num = <32>;
7639 out-ports {
7642 remote-endpoint = <&llcc_tpda_in0>;
7649 compatible = "qcom,coresight-tpdm", "arm,primecell";
7653 clock-names = "apb_pclk";
7655 qcom,cmb-element-bits = <32>;
7656 qcom,cmb-msrs-num = <32>;
7658 out-ports {
7661 remote-endpoint = <&llcc_tpda_in1>;
7668 compatible = "qcom,coresight-tpdm", "arm,primecell";
7672 clock-names = "apb_pclk";
7674 qcom,cmb-element-bits = <32>;
7675 qcom,cmb-msrs-num = <32>;
7677 out-ports {
7680 remote-endpoint = <&llcc_tpda_in2>;
7687 compatible = "qcom,coresight-tpdm", "arm,primecell";
7691 clock-names = "apb_pclk";
7693 qcom,cmb-element-bits = <32>;
7694 qcom,cmb-msrs-num = <32>;
7696 out-ports {
7699 remote-endpoint = <&llcc_tpda_in3>;
7706 compatible = "qcom,coresight-tpdm", "arm,primecell";
7710 clock-names = "apb_pclk";
7712 qcom,cmb-element-bits = <32>;
7713 qcom,cmb-msrs-num = <32>;
7715 out-ports {
7718 remote-endpoint = <&llcc_tpda_in4>;
7725 compatible = "qcom,coresight-tpdm", "arm,primecell";
7729 clock-names = "apb_pclk";
7731 qcom,cmb-element-bits = <32>;
7732 qcom,cmb-msrs-num = <32>;
7734 out-ports {
7737 remote-endpoint = <&llcc_tpda_in5>;
7744 compatible = "qcom,coresight-tpdm", "arm,primecell";
7748 clock-names = "apb_pclk";
7750 qcom,cmb-element-bits = <32>;
7751 qcom,cmb-msrs-num = <32>;
7753 out-ports {
7756 remote-endpoint = <&llcc_tpda_in6>;
7763 compatible = "qcom,coresight-tpdm", "arm,primecell";
7767 clock-names = "apb_pclk";
7769 qcom,cmb-element-bits = <32>;
7770 qcom,cmb-msrs-num = <32>;
7772 out-ports {
7775 remote-endpoint = <&llcc_tpda_in7>;
7782 compatible = "qcom,coresight-tpda", "arm,primecell";
7786 clock-names = "apb_pclk";
7788 in-ports {
7789 #address-cells = <1>;
7790 #size-cells = <0>;
7796 remote-endpoint = <&llcc0_tpdm_out>;
7804 remote-endpoint = <&llcc1_tpdm_out>;
7812 remote-endpoint = <&llcc2_tpdm_out>;
7820 remote-endpoint = <&llcc3_tpdm_out>;
7828 remote-endpoint = <&llcc4_tpdm_out>;
7836 remote-endpoint = <&llcc5_tpdm_out>;
7844 remote-endpoint = <&llcc6_tpdm_out>;
7852 remote-endpoint = <&llcc7_tpdm_out>;
7857 out-ports {
7860 remote-endpoint = <&ddr_funnel1_in0>;
7867 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7871 clock-names = "apb_pclk";
7873 in-ports {
7876 remote-endpoint = <&llcc_tpda_out>;
7881 out-ports {
7884 remote-endpoint = <&ddr_funnel0_in6>;
7891 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
7992 #iommu-cells = <2>;
7993 #global-interrupts = <1>;
7995 dma-coherent;
7999 compatible = "arm,smmu-v3";
8001 #iommu-cells = <1>;
8005 interrupt-names = "eventq",
8007 "cmdq-sync";
8008 dma-coherent;
8012 intc: interrupt-controller@17000000 {
8013 compatible = "arm,gic-v3";
8019 #interrupt-cells = <3>;
8020 interrupt-controller;
8022 #redistributor-regions = <1>;
8023 redistributor-stride = <0x0 0x40000>;
8025 #address-cells = <2>;
8026 #size-cells = <2>;
8029 gic_its: msi-controller@17040000 {
8030 compatible = "arm,gic-v3-its";
8033 msi-controller;
8034 #msi-cells = <1>;
8039 compatible = "qcom,x1e80100-cpucp-mbox";
8042 #mbox-cells = <1>;
8046 compatible = "qcom,rpmh-rsc";
8050 reg-names = "drv-0", "drv-1", "drv-2";
8055 qcom,tcs-offset = <0xd00>;
8056 qcom,drv-id = <2>;
8057 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
8061 power-domains = <&system_pd>;
8063 apps_bcm_voter: bcm-voter {
8064 compatible = "qcom,bcm-voter";
8067 rpmhcc: clock-controller {
8068 compatible = "qcom,x1e80100-rpmh-clk";
8071 clock-names = "xo";
8073 #clock-cells = <1>;
8076 rpmhpd: power-controller {
8077 compatible = "qcom,x1e80100-rpmhpd";
8079 operating-points-v2 = <&rpmhpd_opp_table>;
8081 #power-domain-cells = <1>;
8083 rpmhpd_opp_table: opp-table {
8084 compatible = "operating-points-v2";
8086 rpmhpd_opp_ret: opp-16 {
8087 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
8090 rpmhpd_opp_min_svs: opp-48 {
8091 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
8094 rpmhpd_opp_low_svs_d2: opp-52 {
8095 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
8098 rpmhpd_opp_low_svs_d1: opp-56 {
8099 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
8102 rpmhpd_opp_low_svs_d0: opp-60 {
8103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
8106 rpmhpd_opp_low_svs: opp-64 {
8107 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
8110 rpmhpd_opp_low_svs_l1: opp-80 {
8111 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
8114 rpmhpd_opp_svs: opp-128 {
8115 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
8118 rpmhpd_opp_svs_l0: opp-144 {
8119 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
8122 rpmhpd_opp_svs_l1: opp-192 {
8123 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
8126 rpmhpd_opp_nom: opp-256 {
8127 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
8130 rpmhpd_opp_nom_l1: opp-320 {
8131 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
8134 rpmhpd_opp_nom_l2: opp-336 {
8135 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
8138 rpmhpd_opp_turbo: opp-384 {
8139 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
8142 rpmhpd_opp_turbo_l1: opp-416 {
8143 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
8150 compatible = "arm,armv7-timer-mem";
8153 #address-cells = <2>;
8154 #size-cells = <1>;
8164 frame-number = <0>;
8172 frame-number = <1>;
8182 frame-number = <2>;
8192 frame-number = <3>;
8202 frame-number = <4>;
8212 frame-number = <5>;
8222 frame-number = <6>;
8229 compatible = "mmio-sram";
8232 #address-cells = <1>;
8233 #size-cells = <1>;
8236 cpu_scp_lpri0: scp-sram-section@0 {
8237 compatible = "arm,scmi-shmem";
8241 cpu_scp_lpri1: scp-sram-section@200 {
8242 compatible = "arm,scmi-shmem";
8248 compatible = "arm,sbsa-gwdt";
8255 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
8263 operating-points-v2 = <&llcc_bwmon_opp_table>;
8265 llcc_bwmon_opp_table: opp-table {
8266 compatible = "operating-points-v2";
8268 opp-0 {
8269 opp-peak-kBps = <800000>;
8272 opp-1 {
8273 opp-peak-kBps = <2188000>;
8276 opp-2 {
8277 opp-peak-kBps = <3072000>;
8280 opp-3 {
8281 opp-peak-kBps = <6220800>;
8284 opp-4 {
8285 opp-peak-kBps = <6835200>;
8288 opp-5 {
8289 opp-peak-kBps = <8371200>;
8292 opp-6 {
8293 opp-peak-kBps = <10944000>;
8296 opp-7 {
8297 opp-peak-kBps = <12748800>;
8300 opp-8 {
8301 opp-peak-kBps = <14745600>;
8304 opp-9 {
8305 opp-peak-kBps = <16896000>;
8312 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8320 operating-points-v2 = <&cpu_bwmon_opp_table>;
8325 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8333 operating-points-v2 = <&cpu_bwmon_opp_table>;
8335 cpu_bwmon_opp_table: opp-table {
8336 compatible = "operating-points-v2";
8338 opp-0 {
8339 opp-peak-kBps = <4800000>;
8342 opp-1 {
8343 opp-peak-kBps = <7464000>;
8346 opp-2 {
8347 opp-peak-kBps = <9600000>;
8350 opp-3 {
8351 opp-peak-kBps = <12896000>;
8354 opp-4 {
8355 opp-peak-kBps = <14928000>;
8358 opp-5 {
8359 opp-peak-kBps = <17064000>;
8366 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8374 operating-points-v2 = <&cpu_bwmon_opp_table>;
8377 system-cache-controller@25000000 {
8378 compatible = "qcom,x1e80100-llcc";
8389 reg-names = "llcc0_base",
8403 compatible = "qcom,x1e80100-cdsp-pas";
8406 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
8411 interrupt-names = "wdog",
8415 "stop-ack";
8418 clock-names = "xo";
8420 power-domains = <&rpmhpd RPMHPD_CX>,
8423 power-domain-names = "cx",
8430 memory-region = <&cdsp_mem>,
8435 qcom,smem-states = <&smp2p_cdsp_out 0>;
8436 qcom,smem-state-names = "stop";
8440 glink-edge {
8441 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
8448 qcom,remote-pid = <5>;
8452 qcom,glink-channels = "fastrpcglink-apps-dsp";
8454 qcom,non-secure-domain;
8455 #address-cells = <1>;
8456 #size-cells = <0>;
8458 compute-cb@1 {
8459 compatible = "qcom,fastrpc-compute-cb";
8462 dma-coherent;
8465 compute-cb@2 {
8466 compatible = "qcom,fastrpc-compute-cb";
8469 dma-coherent;
8472 compute-cb@3 {
8473 compatible = "qcom,fastrpc-compute-cb";
8476 dma-coherent;
8479 compute-cb@4 {
8480 compatible = "qcom,fastrpc-compute-cb";
8483 dma-coherent;
8486 compute-cb@5 {
8487 compatible = "qcom,fastrpc-compute-cb";
8490 dma-coherent;
8493 compute-cb@6 {
8494 compatible = "qcom,fastrpc-compute-cb";
8497 dma-coherent;
8500 compute-cb@7 {
8501 compatible = "qcom,fastrpc-compute-cb";
8504 dma-coherent;
8507 compute-cb@8 {
8508 compatible = "qcom,fastrpc-compute-cb";
8511 dma-coherent;
8514 /* note: compute-cb@9 is secure */
8516 compute-cb@10 {
8517 compatible = "qcom,fastrpc-compute-cb";
8520 dma-coherent;
8523 compute-cb@11 {
8524 compatible = "qcom,fastrpc-compute-cb";
8527 dma-coherent;
8530 compute-cb@12 {
8531 compatible = "qcom,fastrpc-compute-cb";
8534 dma-coherent;
8537 compute-cb@13 {
8538 compatible = "qcom,fastrpc-compute-cb";
8541 dma-coherent;
8549 compatible = "arm,armv8-timer";
8557 thermal_zones: thermal-zones {
8558 aoss0-thermal {
8559 thermal-sensors = <&tsens0 0>;
8562 trip-point0 {
8568 aoss0-critical {
8576 cpu0-0-top-thermal {
8577 thermal-sensors = <&tsens0 1>;
8580 cpu-critical {
8588 cpu0-0-btm-thermal {
8589 thermal-sensors = <&tsens0 2>;
8592 cpu-critical {
8600 cpu0-1-top-thermal {
8601 thermal-sensors = <&tsens0 3>;
8604 cpu-critical {
8612 cpu0-1-btm-thermal {
8613 thermal-sensors = <&tsens0 4>;
8616 cpu-critical {
8624 cpu0-2-top-thermal {
8625 thermal-sensors = <&tsens0 5>;
8628 cpu-critical {
8636 cpu0-2-btm-thermal {
8637 thermal-sensors = <&tsens0 6>;
8640 cpu-critical {
8648 cpu0-3-top-thermal {
8649 thermal-sensors = <&tsens0 7>;
8652 cpu-critical {
8660 cpu0-3-btm-thermal {
8661 thermal-sensors = <&tsens0 8>;
8664 cpu-critical {
8672 cpuss0-top-thermal {
8673 thermal-sensors = <&tsens0 9>;
8676 cpuss2-critical {
8684 cpuss0-btm-thermal {
8685 thermal-sensors = <&tsens0 10>;
8688 cpuss2-critical {
8696 mem-thermal {
8697 thermal-sensors = <&tsens0 11>;
8700 trip-point0 {
8706 mem-critical {
8714 video-thermal {
8715 thermal-sensors = <&tsens0 12>;
8718 trip-point0 {
8724 video-critical {
8732 aoss1-thermal {
8733 thermal-sensors = <&tsens1 0>;
8736 trip-point0 {
8742 aoss0-critical {
8750 cpu1-0-top-thermal {
8751 thermal-sensors = <&tsens1 1>;
8754 cpu-critical {
8762 cpu1-0-btm-thermal {
8763 thermal-sensors = <&tsens1 2>;
8766 cpu-critical {
8774 cpu1-1-top-thermal {
8775 thermal-sensors = <&tsens1 3>;
8778 cpu-critical {
8786 cpu1-1-btm-thermal {
8787 thermal-sensors = <&tsens1 4>;
8790 cpu-critical {
8798 cpu1-2-top-thermal {
8799 thermal-sensors = <&tsens1 5>;
8802 cpu-critical {
8810 cpu1-2-btm-thermal {
8811 thermal-sensors = <&tsens1 6>;
8814 cpu-critical {
8822 cpu1-3-top-thermal {
8823 thermal-sensors = <&tsens1 7>;
8826 cpu-critical {
8834 cpu1-3-btm-thermal {
8835 thermal-sensors = <&tsens1 8>;
8838 cpu-critical {
8846 cpuss1-top-thermal {
8847 thermal-sensors = <&tsens1 9>;
8850 cpuss2-critical {
8858 cpuss1-btm-thermal {
8859 thermal-sensors = <&tsens1 10>;
8862 cpuss2-critical {
8870 aoss2-thermal {
8871 thermal-sensors = <&tsens2 0>;
8874 trip-point0 {
8880 aoss0-critical {
8888 cpu2-0-top-thermal {
8889 thermal-sensors = <&tsens2 1>;
8892 cpu-critical {
8900 cpu2-0-btm-thermal {
8901 thermal-sensors = <&tsens2 2>;
8904 cpu-critical {
8912 cpu2-1-top-thermal {
8913 thermal-sensors = <&tsens2 3>;
8916 cpu-critical {
8924 cpu2-1-btm-thermal {
8925 thermal-sensors = <&tsens2 4>;
8928 cpu-critical {
8936 cpu2-2-top-thermal {
8937 thermal-sensors = <&tsens2 5>;
8940 cpu-critical {
8948 cpu2-2-btm-thermal {
8949 thermal-sensors = <&tsens2 6>;
8952 cpu-critical {
8960 cpu2-3-top-thermal {
8961 thermal-sensors = <&tsens2 7>;
8964 cpu-critical {
8972 cpu2-3-btm-thermal {
8973 thermal-sensors = <&tsens2 8>;
8976 cpu-critical {
8984 cpuss2-top-thermal {
8985 thermal-sensors = <&tsens2 9>;
8988 cpuss2-critical {
8996 cpuss2-btm-thermal {
8997 thermal-sensors = <&tsens2 10>;
9000 cpuss2-critical {
9008 aoss3-thermal {
9009 thermal-sensors = <&tsens3 0>;
9012 trip-point0 {
9018 aoss0-critical {
9026 nsp0-thermal {
9027 thermal-sensors = <&tsens3 1>;
9030 trip-point0 {
9036 nsp0-critical {
9044 nsp1-thermal {
9045 thermal-sensors = <&tsens3 2>;
9048 trip-point0 {
9054 nsp1-critical {
9062 nsp2-thermal {
9063 thermal-sensors = <&tsens3 3>;
9066 trip-point0 {
9072 nsp2-critical {
9080 nsp3-thermal {
9081 thermal-sensors = <&tsens3 4>;
9084 trip-point0 {
9090 nsp3-critical {
9098 gpuss-0-thermal {
9099 polling-delay-passive = <200>;
9101 thermal-sensors = <&tsens3 5>;
9103 cooling-maps {
9106 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9111 gpuss0_alert0: trip-point0 {
9117 gpu-critical {
9125 gpuss-1-thermal {
9126 polling-delay-passive = <200>;
9128 thermal-sensors = <&tsens3 6>;
9130 cooling-maps {
9133 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9138 gpuss1_alert0: trip-point0 {
9144 gpu-critical {
9152 gpuss-2-thermal {
9153 polling-delay-passive = <200>;
9155 thermal-sensors = <&tsens3 7>;
9157 cooling-maps {
9160 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9165 gpuss2_alert0: trip-point0 {
9171 gpu-critical {
9179 gpuss-3-thermal {
9180 polling-delay-passive = <200>;
9182 thermal-sensors = <&tsens3 8>;
9184 cooling-maps {
9187 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9192 gpuss3_alert0: trip-point0 {
9198 gpu-critical {
9206 gpuss-4-thermal {
9207 polling-delay-passive = <200>;
9209 thermal-sensors = <&tsens3 9>;
9211 cooling-maps {
9214 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9219 gpuss4_alert0: trip-point0 {
9225 gpu-critical {
9233 gpuss-5-thermal {
9234 polling-delay-passive = <200>;
9236 thermal-sensors = <&tsens3 10>;
9238 cooling-maps {
9241 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9246 gpuss5_alert0: trip-point0 {
9252 gpu-critical {
9260 gpuss-6-thermal {
9261 polling-delay-passive = <200>;
9263 thermal-sensors = <&tsens3 11>;
9265 cooling-maps {
9268 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9273 gpuss6_alert0: trip-point0 {
9279 gpu-critical {
9287 gpuss-7-thermal {
9288 polling-delay-passive = <200>;
9290 thermal-sensors = <&tsens3 12>;
9292 cooling-maps {
9295 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9300 gpuss7_alert0: trip-point0 {
9306 gpu-critical {
9314 camera0-thermal {
9315 thermal-sensors = <&tsens3 13>;
9318 trip-point0 {
9324 camera0-critical {
9332 camera1-thermal {
9333 thermal-sensors = <&tsens3 14>;
9336 trip-point0 {
9342 camera0-critical {