Lines Matching +full:0 +full:x009a0000
29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
50 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
70 reg = <0x0 0x300>;
80 reg = <0x0 0x400>;
90 reg = <0x0 0x500>;
100 reg = <0x0 0x10000>;
116 reg = <0x0 0x10100>;
164 cluster0_c4: cpu-sleep-0 {
167 arm,psci-suspend-param = <0x00000004>;
176 arm,psci-suspend-param = <0x00000004>;
184 cluster_cl5: cluster-sleep-0 {
186 arm,psci-suspend-param = <0x01000054>;
192 domain_ss3: domain-sleep-0 {
194 arm,psci-suspend-param = <0x0200c354>;
210 clk_virt: interconnect-0 {
225 reg = <0x0 0xa0000000 0x0 0x0>;
238 #power-domain-cells = <0>;
244 #power-domain-cells = <0>;
250 #power-domain-cells = <0>;
256 #power-domain-cells = <0>;
262 #power-domain-cells = <0>;
268 #power-domain-cells = <0>;
274 #power-domain-cells = <0>;
280 #power-domain-cells = <0>;
286 #power-domain-cells = <0>;
292 #power-domain-cells = <0>;
298 #power-domain-cells = <0>;
309 reg = <0x0 0x80000000 0x0 0xe00000>;
314 reg = <0x0 0x80e00000 0x0 0x40000>;
319 reg = <0x0 0x81200000 0x0 0x200000>;
324 reg = <0x0 0x81a00000 0x0 0x40000>;
329 reg = <0x0 0x81c00000 0x0 0x60000>;
335 reg = <0x0 0x81c60000 0x0 0x20000>;
341 reg = <0x0 0x81c80000 0x0 0x74000>;
349 reg = <0x0 0x81d00000 0x0 0x200000>;
355 reg = <0x0 0x81f00000 0x0 0x100000>;
360 reg = <0x0 0x82000000 0x0 0x380000>;
365 reg = <0x0 0x82380000 0x0 0x20000>;
370 reg = <0x0 0x823a0000 0x0 0x40000>;
375 reg = <0x0 0x823e0000 0x0 0x80000>;
380 reg = <0x0 0x824a0000 0x0 0x100000>;
385 reg = <0x0 0x82600000 0x0 0x100000>;
390 reg = <0x0 0x82700000 0x0 0x100000>;
395 reg = <0x0 0x82800000 0x0 0x2000000>;
400 reg = <0x0 0x84a00000 0x0 0x4900000>;
405 reg = <0x0 0x89300000 0x0 0xa80000>;
410 reg = <0x0 0x8ba00000 0x0 0xf600000>;
415 reg = <0x0 0x9b000000 0x0 0x80000>;
420 reg = <0x0 0x9b080000 0x0 0x10000>;
425 reg = <0x0 0x9b090000 0x0 0xa000>;
430 reg = <0x0 0x9b09a000 0x0 0x2000>;
435 reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
441 reg = <0x0 0x9b280000 0x0 0x40000>;
447 reg = <0x0 0x9b2c0000 0x0 0x40000>;
452 reg = <0x0 0x9b300000 0x0 0x800000>;
457 reg = <0x0 0x9bb00000 0x0 0x800000>;
462 reg = <0x0 0x9c300000 0x0 0x800000>;
467 reg = <0x0 0x9cb00000 0x0 0x700000>;
472 reg = <0x0 0x9d200000 0x0 0x1900000>;
477 reg = <0x0 0x9eb00000 0x0 0x80000>;
482 reg = <0x0 0x9ec00000 0x0 0x180000>;
487 reg = <0x0 0x9ed80000 0x0 0x80000>;
492 reg = <0x0 0x9ee00000 0x0 0x3a80000>;
497 reg = <0x0 0xb8000000 0x0 0x1c0000>;
503 reg = <0x0 0xd4e23000 0x0 0x2dd000>;
508 reg = <0x0 0xd8000000 0x0 0x600000>;
513 reg = <0x0 0xf3800000 0x0 0x4400000>;
518 reg = <0x0 0xf7c00000 0x0 0x4c00000>;
523 reg = <0x0 0xff800000 0x0 0x800000>;
539 qcom,local-pid = <0>;
565 qcom,local-pid = <0>;
591 qcom,local-pid = <0>;
619 soc: soc@0 {
624 dma-ranges = <0 0 0 0 0x10 0>;
625 ranges = <0 0 0 0 0x10 0>;
629 reg = <0x0 0x00100000 0x0 0x1f4200>;
632 <0>,
634 <0>,
635 <0>,
636 <0>,
637 <0>,
638 <0>;
647 reg = <0x0 0x00406000 0x0 0x1000>;
658 reg = <0x0 0x00800000 0x0 0x60000>;
674 dma-channel-mask = <0x1e>;
677 iommus = <&apps_smmu 0x436 0x0>;
684 reg = <0x0 0x008c0000 0x0 0x2000>;
691 iommus = <&apps_smmu 0x423 0x0>;
701 reg = <0x0 0x00880000 0x0 0x4000>;
718 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
719 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
723 pinctrl-0 = <&qup_i2c8_data_clk>;
727 #size-cells = <0>;
734 reg = <0x0 0x00880000 0x0 0x4000>;
751 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
752 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
756 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
760 #size-cells = <0>;
767 reg = <0x0 0x00884000 0x0 0x4000>;
784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
789 pinctrl-0 = <&qup_i2c9_data_clk>;
793 #size-cells = <0>;
800 reg = <0x0 0x00884000 0x0 0x4000>;
817 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
822 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
826 #size-cells = <0>;
833 reg = <0x0 0x00888000 0x0 0x4000>;
850 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
855 pinctrl-0 = <&qup_i2c10_data_clk>;
859 #size-cells = <0>;
866 reg = <0x0 0x00888000 0x0 0x4000>;
883 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
888 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
892 #size-cells = <0>;
899 reg = <0x0 0x0088c000 0x0 0x4000>;
916 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
921 pinctrl-0 = <&qup_i2c11_data_clk>;
925 #size-cells = <0>;
932 reg = <0x0 0x0088c000 0x0 0x4000>;
949 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
954 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
958 #size-cells = <0>;
965 reg = <0x0 0x00890000 0x0 0x4000>;
982 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
987 pinctrl-0 = <&qup_i2c12_data_clk>;
991 #size-cells = <0>;
998 reg = <0x0 0x00890000 0x0 0x4000>;
1015 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1020 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1024 #size-cells = <0>;
1031 reg = <0x0 0x00894000 0x0 0x4000>;
1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1053 pinctrl-0 = <&qup_i2c13_data_clk>;
1057 #size-cells = <0>;
1064 reg = <0x0 0x00894000 0x0 0x4000>;
1081 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1086 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1090 #size-cells = <0>;
1097 reg = <0x0 0x00898000 0x0 0x4000>;
1111 pinctrl-0 = <&qup_uart14_default>;
1119 reg = <0x0 0x0089c000 0x0 0x4000>;
1136 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1141 pinctrl-0 = <&qup_i2c15_data_clk>;
1145 #size-cells = <0>;
1152 reg = <0x0 0x0089c000 0x0 0x4000>;
1169 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1174 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1178 #size-cells = <0>;
1186 reg = <0x0 0x009c0000 0x0 0x2000>;
1199 reg = <0x0 0x00980000 0x0 0x4000>;
1215 pinctrl-0 = <&hub_i2c0_data_clk>;
1219 #size-cells = <0>;
1226 reg = <0x0 0x00984000 0x0 0x4000>;
1242 pinctrl-0 = <&hub_i2c1_data_clk>;
1246 #size-cells = <0>;
1253 reg = <0x0 0x00988000 0x0 0x4000>;
1269 pinctrl-0 = <&hub_i2c2_data_clk>;
1273 #size-cells = <0>;
1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1296 pinctrl-0 = <&hub_i2c3_data_clk>;
1300 #size-cells = <0>;
1307 reg = <0x0 0x00990000 0x0 0x4000>;
1323 pinctrl-0 = <&hub_i2c4_data_clk>;
1327 #size-cells = <0>;
1334 reg = <0x0 0x00994000 0x0 0x4000>;
1350 pinctrl-0 = <&hub_i2c5_data_clk>;
1354 #size-cells = <0>;
1361 reg = <0x0 0x00998000 0x0 0x4000>;
1377 pinctrl-0 = <&hub_i2c6_data_clk>;
1381 #size-cells = <0>;
1388 reg = <0x0 0x0099c000 0x0 0x4000>;
1404 pinctrl-0 = <&hub_i2c7_data_clk>;
1408 #size-cells = <0>;
1415 reg = <0x0 0x009a0000 0x0 0x4000>;
1431 pinctrl-0 = <&hub_i2c8_data_clk>;
1435 #size-cells = <0>;
1442 reg = <0x0 0x009a4000 0x0 0x4000>;
1458 pinctrl-0 = <&hub_i2c9_data_clk>;
1462 #size-cells = <0>;
1470 reg = <0x0 0x00a00000 0x0 0x60000>;
1486 dma-channel-mask = <0x1e>;
1489 iommus = <&apps_smmu 0xb6 0x0>;
1496 reg = <0x0 0x00ac0000 0x0 0x2000>;
1503 iommus = <&apps_smmu 0xa3 0x0>;
1513 reg = <0x0 0x00a80000 0x0 0x4000>;
1530 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1531 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1535 pinctrl-0 = <&qup_i2c0_data_clk>;
1539 #size-cells = <0>;
1546 reg = <0x0 0x00a80000 0x0 0x4000>;
1563 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1564 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1568 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1572 #size-cells = <0>;
1579 reg = <0x0 0x00a84000 0x0 0x4000>;
1596 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1601 pinctrl-0 = <&qup_i2c1_data_clk>;
1605 #size-cells = <0>;
1612 reg = <0x0 0x00a84000 0x0 0x4000>;
1629 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1634 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1638 #size-cells = <0>;
1645 reg = <0x0 0x00a88000 0x0 0x4000>;
1662 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1667 pinctrl-0 = <&qup_i2c2_data_clk>;
1671 #size-cells = <0>;
1678 reg = <0x0 0x00a88000 0x0 0x4000>;
1695 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1700 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1704 #size-cells = <0>;
1711 reg = <0x0 0x00a8c000 0x0 0x4000>;
1728 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1733 pinctrl-0 = <&qup_i2c3_data_clk>;
1737 #size-cells = <0>;
1744 reg = <0x0 0x00a8c000 0x0 0x4000>;
1761 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1766 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1770 #size-cells = <0>;
1777 reg = <0x0 0x00a90000 0x0 0x4000>;
1794 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1799 pinctrl-0 = <&qup_i2c4_data_clk>;
1803 #size-cells = <0>;
1810 reg = <0x0 0x00a90000 0x0 0x4000>;
1827 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1832 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1836 #size-cells = <0>;
1843 reg = <0x0 0x00a94000 0x0 0x4000>;
1860 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1865 pinctrl-0 = <&qup_i2c5_data_clk>;
1869 #size-cells = <0>;
1876 reg = <0x0 0x00a94000 0x0 0x4000>;
1893 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1898 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1902 #size-cells = <0>;
1909 reg = <0x0 0x00a98000 0x0 0x4000>;
1926 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1931 pinctrl-0 = <&qup_i2c6_data_clk>;
1935 #size-cells = <0>;
1942 reg = <0x0 0x00a98000 0x0 0x4000>;
1959 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1964 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1968 #size-cells = <0>;
1975 reg = <0x0 0x00a9c000 0x0 0x4000>;
1989 pinctrl-0 = <&qup_uart7_default>;
1998 reg = <0x0 0x010c3000 0x0 0x1000>;
2003 reg = <0x0 0x01500000 0x0 0x16080>;
2010 reg = <0x0 0x01600000 0x0 0x6200>;
2017 reg = <0x0 0x01680000 0x0 0x1d080>;
2024 reg = <0x0 0x016c0000 0x0 0x11400>;
2033 reg = <0x0 0x016e0000 0x0 0x16400>;
2042 reg = <0x0 0x01700000 0x0 0x1f400>;
2050 reg = <0x0 0x01780000 0x0 0x5b800>;
2058 reg = <0x0 0x01d88000 0x0 0x18000>;
2065 reg = <0x0 0x01dc4000 0x0 0x28000>;
2071 iommus = <&apps_smmu 0x480 0>,
2072 <&apps_smmu 0x481 0>;
2074 qcom,ee = <0>;
2080 reg = <0x0 0x01dfa000 0x0 0x6000>;
2089 iommus = <&apps_smmu 0x480 0>,
2090 <&apps_smmu 0x481 0>;
2095 reg = <0x0 0x01f40000 0x0 0x20000>;
2101 reg = <0x0 0x04080000 0x0 0x10000>;
2104 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2133 qcom,smem-states = <&smp2p_modem_out 0>;
2154 reg = <0x0 0x06800000 0x0 0x10000>;
2157 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2184 qcom,smem-states = <&smp2p_adsp_out 0>;
2204 #size-cells = <0>;
2209 #sound-dai-cells = <0>;
2220 iommus = <&apps_smmu 0x1001 0x80>,
2221 <&apps_smmu 0x1041 0x20>;
2242 reg = <0x0 0x06aa0000 0x0 0x1000>;
2252 #clock-cells = <0>;
2259 reg = <0x0 0x06ab0000 0x0 0x10000>;
2265 pinctrl-0 = <&wsa2_swr_active>;
2271 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
2272 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2273 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2274 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2275 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2276 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
2277 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2279 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2282 #size-cells = <0>;
2289 reg = <0x0 0x06ac0000 0x0 0x1000>;
2299 #clock-cells = <0>;
2306 reg = <0x0 0x06ad0000 0x0 0x10000>;
2312 pinctrl-0 = <&rx_swr_active>;
2318 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>;
2319 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2320 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2321 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>;
2322 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>;
2323 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>;
2324 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2325 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
2326 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
2329 #size-cells = <0>;
2336 reg = <0x0 0x06ae0000 0x0 0x1000>;
2346 #clock-cells = <0>;
2353 reg = <0x0 0x06b00000 0x0 0x1000>;
2363 #clock-cells = <0>;
2370 reg = <0x0 0x06b10000 0x0 0x10000>;
2376 pinctrl-0 = <&wsa_swr_active>;
2382 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
2383 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
2384 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2385 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2386 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
2387 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
2388 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
2389 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2390 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2393 #size-cells = <0>;
2400 reg = <0x0 0x07e40000 0x0 0xe080>;
2407 reg = <0x0 0x07400000 0x0 0x19080>;
2414 reg = <0x0 0x07420000 0x0 0x44080>;
2421 reg = <0x0 0x07630000 0x0 0x10000>;
2429 pinctrl-0 = <&tx_swr_active>;
2433 qcom,dout-ports = <0>;
2435 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2436 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2437 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2438 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2439 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2440 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2441 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2442 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2443 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2446 #size-cells = <0>;
2453 reg = <0x0 0x07660000 0x0 0x2000>;
2461 #clock-cells = <0>;
2469 reg = <0x0 0x07760000 0x0 0x20000>;
2477 gpio-ranges = <&lpass_tlmm 0 0 23>;
2586 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
2588 qcom,pdc-ranges = <0 745 51>, <51 527 47>,
2598 reg = <0x0 0x0c300000 0x0 0x400>;
2606 #clock-cells = <0>;
2611 reg = <0x0 0x0c3f0000 0x0 0x400>;
2617 reg = <0x0 0x0c400000 0x0 0x3000>,
2618 <0x0 0x0c500000 0x0 0x400000>,
2619 <0x0 0x0c440000 0x0 0x80000>,
2620 <0x0 0x0c4c0000 0x0 0x10000>,
2621 <0x0 0x0c42d000 0x0 0x4000>;
2631 qcom,ee = <0>;
2632 qcom,channel = <0>;
2633 qcom,bus-id = <0>;
2639 #size-cells = <0>;
2644 reg = <0x0 0x0f100000 0x0 0x102000>;
2654 gpio-ranges = <&tlmm 0 0 216>;
3149 reg = <0x0 0x0f204008 0x0 0x3004>;
3159 reg = <0x0 0x15000000 0x0 0x100000>;
3283 reg = <0x0 0x16000000 0x0 0x10000>,
3284 <0x0 0x16080000 0x0 0x200000>;
3292 redistributor-stride = <0x0 0x40000>;
3300 reg = <0x0 0x16040000 0x0 0x20000>;
3309 reg = <0x0 0x01d80000 0x0 0x2000>;
3319 resets = <&ufs_mem_hc 0>;
3325 #phy-cells = <0>;
3332 reg = <0x0 0x01d84000 0x0 0x3000>;
3368 iommus = <&apps_smmu 0x60 0>;
3385 /bits/ 64 <0>,
3386 /bits/ 64 <0>,
3388 /bits/ 64 <0>,
3389 /bits/ 64 <0>,
3390 /bits/ 64 <0>,
3391 /bits/ 64 <0>;
3397 /bits/ 64 <0>,
3398 /bits/ 64 <0>,
3400 /bits/ 64 <0>,
3401 /bits/ 64 <0>,
3402 /bits/ 64 <0>,
3403 /bits/ 64 <0>;
3411 reg = <0x0 0x16500000 0x0 0x10000>,
3412 <0x0 0x16510000 0x0 0x10000>,
3413 <0x0 0x16520000 0x0 0x10000>;
3414 reg-names = "drv-0",
3421 qcom,tcs-offset = <0xd00>;
3424 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3543 reg = <0x0 0x16800000 0x0 0x1000>;
3547 ranges = <0 0 0 0 0x20000000>;
3550 reg = <0x0 0x16801000 0x1000>,
3551 <0x0 0x16802000 0x1000>;
3556 frame-number = <0>;
3560 reg = <0x0 0x16803000 0x1000>;
3570 reg = <0x0 0x16805000 0x1000>;
3580 reg = <0x0 0x16807000 0x1000>;
3590 reg = <0x0 0x16809000 0x1000>;
3600 reg = <0x0 0x1680b000 0x1000>;
3610 reg = <0x0 0x1680d000 0x1000>;
3622 reg = <0x0 0x24100000 0x0 0x14b080>;
3629 reg = <0x0 0x24800000 0x0 0x200000>,
3630 <0x0 0x25800000 0x0 0x200000>,
3631 <0x0 0x24c00000 0x0 0x200000>,
3632 <0x0 0x25c00000 0x0 0x200000>,
3633 <0x0 0x26800000 0x0 0x200000>,
3634 <0x0 0x26c00000 0x0 0x200000>;
3647 reg = <0x0 0x320c0000 0x0 0x13080>;
3654 reg = <0x0 0x32300000 0x0 0x10000>;
3657 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3684 qcom,smem-states = <&smp2p_cdsp_out 0>;
3704 #size-cells = <0>;
3709 iommus = <&apps_smmu 0x19c1 0x0>,
3710 <&apps_smmu 0x0c21 0x0>,
3711 <&apps_smmu 0x0c01 0x40>;
3718 iommus = <&apps_smmu 0x1962 0x0>,
3719 <&apps_smmu 0x0c02 0x20>,
3720 <&apps_smmu 0x0c42 0x0>,
3721 <&apps_smmu 0x19c2 0x0>;
3728 iommus = <&apps_smmu 0x1963 0x0>,
3729 <&apps_smmu 0x0c23 0x0>,
3730 <&apps_smmu 0x0c03 0x40>,
3731 <&apps_smmu 0x19c3 0x0>;
3738 iommus = <&apps_smmu 0x1964 0x0>,
3739 <&apps_smmu 0x0c24 0x0>,
3740 <&apps_smmu 0x0c04 0x40>,
3741 <&apps_smmu 0x19c4 0x0>;
3748 iommus = <&apps_smmu 0x1965 0x0>,
3749 <&apps_smmu 0x0c25 0x0>,
3750 <&apps_smmu 0x0c05 0x40>,
3751 <&apps_smmu 0x19c5 0x0>;
3758 iommus = <&apps_smmu 0x1966 0x0>,
3759 <&apps_smmu 0x0c06 0x20>,
3760 <&apps_smmu 0x0c46 0x0>,
3761 <&apps_smmu 0x19c6 0x0>;
3768 iommus = <&apps_smmu 0x1967 0x0>,
3769 <&apps_smmu 0x0c27 0x0>,
3770 <&apps_smmu 0x0c07 0x40>,
3771 <&apps_smmu 0x19c7 0x0>;
3778 iommus = <&apps_smmu 0x1968 0x0>,
3779 <&apps_smmu 0x0c08 0x20>,
3780 <&apps_smmu 0x0c48 0x0>,
3781 <&apps_smmu 0x19c8 0x0>;
3790 iommus = <&apps_smmu 0x196c 0x0>,
3791 <&apps_smmu 0x0c2c 0x20>,
3792 <&apps_smmu 0x0c0c 0x40>,
3793 <&apps_smmu 0x19cc 0x0>;
3800 iommus = <&apps_smmu 0x196d 0x0>,
3801 <&apps_smmu 0x0c0d 0x20>,
3802 <&apps_smmu 0x0c2e 0x0>,
3803 <&apps_smmu 0x0c4d 0x0>,
3804 <&apps_smmu 0x19cd 0x0>;
3811 iommus = <&apps_smmu 0x196e 0x0>,
3812 <&apps_smmu 0x0c0e 0x20>,
3813 <&apps_smmu 0x19ce 0x0>;