Lines Matching +full:0 +full:x00884000
40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
99 clocks = <&cpufreq_hw 0>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
119 reg = <0 0x200>;
120 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
140 reg = <0 0x300>;
161 reg = <0 0x400>;
182 reg = <0 0x500>;
203 reg = <0 0x600>;
224 reg = <0 0x700>;
281 little_cpu_sleep_0: cpu-sleep-0-0 {
284 arm,psci-suspend-param = <0x40000004>;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
294 arm,psci-suspend-param = <0x40000004>;
301 prime_cpu_sleep_0: cpu-sleep-2-0 {
304 arm,psci-suspend-param = <0x40000004>;
313 cluster_sleep_0: cluster-sleep-0 {
315 arm,psci-suspend-param = <0x41000044>;
323 arm,psci-suspend-param = <0x4100c344>;
334 qcom,dload-mode = <&tcsr 0x19000>;
340 clk_virt: interconnect-0 {
397 reg = <0 0xa0000000 0 0>;
425 #power-domain-cells = <0>;
431 #power-domain-cells = <0>;
437 #power-domain-cells = <0>;
443 #power-domain-cells = <0>;
449 #power-domain-cells = <0>;
455 #power-domain-cells = <0>;
461 #power-domain-cells = <0>;
467 #power-domain-cells = <0>;
473 #power-domain-cells = <0>;
484 reg = <0 0x80000000 0 0xa00000>;
489 reg = <0 0x80a00000 0 0x400000>;
494 reg = <0 0x80e00000 0 0x3d0000>;
499 reg = <0 0xd8100000 0 0x40000>;
504 reg = <0 0x811d0000 0 0x30000>;
510 reg = <0 0x81a00000 0 0x260000>;
516 reg = <0 0x81c60000 0 0x20000>;
522 reg = <0 0x81c80000 0 0x74000>;
529 reg = <0 0x81d00000 0 0x200000>;
535 reg = <0 0x81f00000 0 0x20000>;
540 reg = <0 0x82600000 0 0x100000>;
545 reg = <0 0x82700000 0 0x100000>;
550 reg = <0 0x82800000 0 0x4600000>;
555 reg = <0 0x8a800000 0 0x10800000>;
560 reg = <0 0x9b000000 0 0x80000>;
565 reg = <0 0x9b080000 0 0x10000>;
570 reg = <0 0x9b090000 0 0xa000>;
575 reg = <0 0x9b09a000 0 0x2000>;
580 reg = <0 0x9b100000 0 0x180000>;
586 reg = <0 0x9b280000 0 0x60000>;
592 reg = <0 0x9b2e0000 0 0x20000>;
597 reg = <0 0x9b300000 0 0x800000>;
602 reg = <0 0x9bb00000 0 0x700000>;
607 reg = <0 0x9c200000 0 0x700000>;
612 reg = <0 0x9c900000 0 0x2000000>;
617 reg = <0 0x9e900000 0 0x80000>;
622 reg = <0 0x9e980000 0 0x80000>;
627 reg = <0 0x9ea00000 0 0x4080000>;
633 /* Linux kernel image is loaded at 0xa8000000 */
637 reg = <0x0 0xd4a80000 0x0 0x280000>;
645 reg = <0 0xd4d00000 0 0x3300000>;
650 reg = <0 0xd8000000 0 0x100000>;
655 reg = <0 0xd8140000 0 0x1c0000>;
660 reg = <0 0xd8300000 0 0x500000>;
665 reg = <0 0xd8800000 0 0x8a00000>;
670 reg = <0 0xe1200000 0 0x2740000>;
675 reg = <0 0xe6440000 0 0x279000>;
680 reg = <0 0xf3600000 0 0x4aee000>;
685 reg = <0 0xf80ee000 0 0x1000>;
690 reg = <0 0xf80ef000 0 0x9000>;
695 reg = <0 0xf80f8000 0 0x4000>;
700 reg = <0 0xf80fc000 0 0x4000>;
705 reg = <0 0xf8100000 0 0x100000>;
710 reg = <0 0xf8400000 0 0x4800000>;
715 reg = <0 0xfcc00000 0 0x4000>;
720 reg = <0 0xfcc04000 0 0x100000>;
725 reg = <0 0xfce00000 0 0x2900000>;
730 reg = <0 0xff700000 0 0x100000>;
744 qcom,local-pid = <0>;
768 qcom,local-pid = <0>;
792 qcom,local-pid = <0>;
818 soc: soc@0 {
820 ranges = <0 0 0 0 0x10 0>;
821 dma-ranges = <0 0 0 0 0x10 0>;
828 reg = <0 0x00100000 0 0x1f4200>;
836 <&ufs_mem_phy 0>,
844 reg = <0 0x00408000 0 0x1000>;
854 reg = <0 0x00800000 0 0x60000>;
868 dma-channel-mask = <0x3e>;
869 iommus = <&apps_smmu 0x436 0>;
876 reg = <0 0x008c0000 0 0x2000>;
881 iommus = <&apps_smmu 0x423 0>;
889 reg = <0 0x00880000 0 0x4000>;
893 pinctrl-0 = <&qup_i2c8_data_clk>;
896 #size-cells = <0>;
904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
905 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
914 reg = <0 0x00880000 0 0x4000>;
919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
928 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
933 #size-cells = <0>;
939 reg = <0 0x00884000 0 0x4000>;
943 pinctrl-0 = <&qup_i2c9_data_clk>;
946 #size-cells = <0>;
954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
964 reg = <0 0x00884000 0 0x4000>;
969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
983 #size-cells = <0>;
989 reg = <0 0x00888000 0 0x4000>;
993 pinctrl-0 = <&qup_i2c10_data_clk>;
996 #size-cells = <0>;
1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1014 reg = <0 0x00888000 0 0x4000>;
1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1033 #size-cells = <0>;
1039 reg = <0 0x0088c000 0 0x4000>;
1043 pinctrl-0 = <&qup_i2c11_data_clk>;
1046 #size-cells = <0>;
1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1064 reg = <0 0x0088c000 0 0x4000>;
1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1083 #size-cells = <0>;
1089 reg = <0 0x00890000 0 0x4000>;
1093 pinctrl-0 = <&qup_i2c12_data_clk>;
1096 #size-cells = <0>;
1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1114 reg = <0 0x00890000 0 0x4000>;
1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1133 #size-cells = <0>;
1139 reg = <0 0x00894000 0 0x4000>;
1143 pinctrl-0 = <&qup_i2c13_data_clk>;
1146 #size-cells = <0>;
1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1164 reg = <0 0x00894000 0 0x4000>;
1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1183 #size-cells = <0>;
1189 reg = <0 0x898000 0 0x4000>;
1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1207 reg = <0 0x0089c000 0 0x4000>;
1211 pinctrl-0 = <&qup_i2c15_data_clk>;
1214 #size-cells = <0>;
1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1232 reg = <0 0x0089c000 0 0x4000>;
1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1251 #size-cells = <0>;
1258 reg = <0x0 0x009c0000 0x0 0x2000>;
1268 reg = <0x0 0x00980000 0x0 0x4000>;
1273 pinctrl-0 = <&hub_i2c0_data_clk>;
1276 #size-cells = <0>;
1289 reg = <0x0 0x00984000 0x0 0x4000>;
1294 pinctrl-0 = <&hub_i2c1_data_clk>;
1297 #size-cells = <0>;
1310 reg = <0x0 0x00988000 0x0 0x4000>;
1315 pinctrl-0 = <&hub_i2c2_data_clk>;
1318 #size-cells = <0>;
1331 reg = <0x0 0x0098c000 0x0 0x4000>;
1336 pinctrl-0 = <&hub_i2c3_data_clk>;
1339 #size-cells = <0>;
1352 reg = <0x0 0x00990000 0x0 0x4000>;
1357 pinctrl-0 = <&hub_i2c4_data_clk>;
1360 #size-cells = <0>;
1373 reg = <0 0x00994000 0 0x4000>;
1378 pinctrl-0 = <&hub_i2c5_data_clk>;
1381 #size-cells = <0>;
1394 reg = <0 0x00998000 0 0x4000>;
1399 pinctrl-0 = <&hub_i2c6_data_clk>;
1402 #size-cells = <0>;
1415 reg = <0 0x0099c000 0 0x4000>;
1420 pinctrl-0 = <&hub_i2c7_data_clk>;
1423 #size-cells = <0>;
1436 reg = <0 0x009a0000 0 0x4000>;
1441 pinctrl-0 = <&hub_i2c8_data_clk>;
1444 #size-cells = <0>;
1457 reg = <0 0x009a4000 0 0x4000>;
1462 pinctrl-0 = <&hub_i2c9_data_clk>;
1465 #size-cells = <0>;
1480 reg = <0 0x00a00000 0 0x60000>;
1494 dma-channel-mask = <0x1e>;
1495 iommus = <&apps_smmu 0xb6 0>;
1502 reg = <0 0x00ac0000 0 0x2000>;
1507 iommus = <&apps_smmu 0xa3 0>;
1518 reg = <0 0x00a80000 0 0x4000>;
1522 pinctrl-0 = <&qup_i2c0_data_clk>;
1525 #size-cells = <0>;
1533 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1543 reg = <0 0x00a80000 0 0x4000>;
1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1562 #size-cells = <0>;
1568 reg = <0 0x00a84000 0 0x4000>;
1572 pinctrl-0 = <&qup_i2c1_data_clk>;
1575 #size-cells = <0>;
1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1593 reg = <0 0x00a84000 0 0x4000>;
1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1612 #size-cells = <0>;
1618 reg = <0 0x00a88000 0 0x4000>;
1622 pinctrl-0 = <&qup_i2c2_data_clk>;
1625 #size-cells = <0>;
1633 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1643 reg = <0 0x00a88000 0 0x4000>;
1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1662 #size-cells = <0>;
1668 reg = <0 0x00a8c000 0 0x4000>;
1672 pinctrl-0 = <&qup_i2c3_data_clk>;
1675 #size-cells = <0>;
1683 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1693 reg = <0 0x00a8c000 0 0x4000>;
1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1712 #size-cells = <0>;
1718 reg = <0 0x00a90000 0 0x4000>;
1722 pinctrl-0 = <&qup_i2c4_data_clk>;
1725 #size-cells = <0>;
1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1743 reg = <0 0x00a90000 0 0x4000>;
1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1756 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1762 #size-cells = <0>;
1768 reg = <0 0x00a94000 0 0x4000>;
1772 pinctrl-0 = <&qup_i2c5_data_clk>;
1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1787 #size-cells = <0>;
1793 reg = <0 0x00a94000 0 0x4000>;
1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1806 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1812 #size-cells = <0>;
1818 reg = <0 0x00a98000 0 0x4000>;
1822 pinctrl-0 = <&qup_i2c6_data_clk>;
1831 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1837 #size-cells = <0>;
1843 reg = <0 0x00a98000 0 0x4000>;
1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1862 #size-cells = <0>;
1868 reg = <0 0x00a9c000 0 0x4000>;
1872 pinctrl-0 = <&qup_uart7_default>;
1887 reg = <0 0x01500000 0 0x13080>;
1894 reg = <0 0x01600000 0 0x6200>;
1901 reg = <0 0x01680000 0 0x1d080>;
1908 reg = <0 0x016c0000 0 0x12200>;
1917 reg = <0 0x016e0000 0 0x14400>;
1926 reg = <0 0x01700000 0 0x1e400>;
1934 reg = <0 0x01780000 0 0x5b800>;
1941 reg = <0 0x010c3000 0 0x1000>;
1947 reg = <0 0x01c00000 0 0x3000>,
1948 <0 0x60000000 0 0xf1d>,
1949 <0 0x60000f20 0 0xa8>,
1950 <0 0x60001000 0 0x1000>,
1951 <0 0x60100000 0 0x100000>;
1955 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1956 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1957 bus-range = <0x00 0xff>;
1961 linux,pci-domain = <0>;
1983 interrupt-map-mask = <0 0 0 0x7>;
1984 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1985 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1986 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1987 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2010 msi-map = <0x0 &gic_its 0x1400 0x1>,
2011 <0x100 &gic_its 0x1401 0x1>;
2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
2013 <0x100 &apps_smmu 0x1401 0x1>;
2066 pcieport0: pcie@0 {
2068 reg = <0x0 0x0 0x0 0x0 0x0>;
2069 bus-range = <0x01 0xff>;
2079 reg = <0 0x01c06000 0 0x2000>;
2097 #clock-cells = <0>;
2100 #phy-cells = <0>;
2108 reg = <0x0 0x01c08000 0x0 0x3000>,
2109 <0x0 0x40000000 0x0 0xf1d>,
2110 <0x0 0x40000f20 0x0 0xa8>,
2111 <0x0 0x40001000 0x0 0x1000>,
2112 <0x0 0x40100000 0x0 0x100000>;
2116 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2117 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2118 bus-range = <0x00 0xff>;
2144 interrupt-map-mask = <0 0 0 0x7>;
2145 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2146 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2147 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2148 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2176 msi-map = <0x0 &gic_its 0x1480 0x1>,
2177 <0x100 &gic_its 0x1481 0x1>;
2178 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
2179 <0x100 &apps_smmu 0x1481 0x1>;
2240 pcie@0 {
2242 reg = <0x0 0x0 0x0 0x0 0x0>;
2243 bus-range = <0x01 0xff>;
2253 reg = <0x0 0x01c0e000 0x0 0x2000>;
2275 #phy-cells = <0>;
2282 reg = <0x0 0x01dc4000 0x0 0x28000>;
2285 qcom,ee = <0>;
2289 iommus = <&apps_smmu 0x480 0x0>,
2290 <&apps_smmu 0x481 0x0>;
2295 reg = <0x0 0x01dfa000 0x0 0x6000>;
2298 iommus = <&apps_smmu 0x480 0x0>,
2299 <&apps_smmu 0x481 0x0>;
2307 reg = <0x0 0x01d80000 0x0 0x2000>;
2317 resets = <&ufs_mem_hc 0>;
2321 #phy-cells = <0>;
2329 reg = <0x0 0x01d84000 0x0 0x3000>;
2341 iommus = <&apps_smmu 0x60 0x0>;
2376 /bits/ 64 <0>,
2377 /bits/ 64 <0>,
2379 /bits/ 64 <0>,
2380 /bits/ 64 <0>,
2381 /bits/ 64 <0>,
2382 /bits/ 64 <0>;
2388 /bits/ 64 <0>,
2389 /bits/ 64 <0>,
2391 /bits/ 64 <0>,
2392 /bits/ 64 <0>,
2393 /bits/ 64 <0>,
2394 /bits/ 64 <0>;
2400 /bits/ 64 <0>,
2401 /bits/ 64 <0>,
2403 /bits/ 64 <0>,
2404 /bits/ 64 <0>,
2405 /bits/ 64 <0>,
2406 /bits/ 64 <0>;
2415 reg = <0 0x01d88000 0 0x18000>;
2422 reg = <0 0x01f40000 0 0x20000>;
2428 reg = <0 0x01fc0000 0 0x30000>;
2436 reg = <0x0 0x03d00000 0x0 0x40000>,
2437 <0x0 0x03d9e000 0x0 0x1000>,
2438 <0x0 0x03d61000 0x0 0x800>;
2445 iommus = <&adreno_smmu 0 0x0>,
2446 <&adreno_smmu 1 0x0>;
2519 reg = <0x0 0x03d6a000 0x0 0x35000>,
2520 <0x0 0x03d50000 0x0 0x10000>,
2521 <0x0 0x0b280000 0x0 0x10000>;
2548 iommus = <&adreno_smmu 5 0x0>;
2571 reg = <0 0x03d90000 0 0xa000>;
2583 reg = <0x0 0x03da0000 0x0 0x40000>;
2627 iommus = <&apps_smmu 0x4a0 0x0>,
2628 <&apps_smmu 0x4a2 0x0>;
2629 reg = <0 0x3f40000 0 0x10000>,
2630 <0 0x3f50000 0 0x5000>,
2631 <0 0x3e04000 0 0xfc000>;
2638 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2657 qcom,smem-states = <&ipa_smp2p_out 0>,
2667 reg = <0x0 0x04080000 0x0 0x10000>;
2670 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2692 qcom,smem-states = <&smp2p_modem_out 0>;
2710 reg = <0x0 0x06800000 0x0 0x10000>;
2713 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2734 qcom,smem-states = <&smp2p_adsp_out 0>;
2755 #size-cells = <0>;
2760 iommus = <&apps_smmu 0x1003 0x80>,
2761 <&apps_smmu 0x1063 0x0>;
2768 iommus = <&apps_smmu 0x1004 0x80>,
2769 <&apps_smmu 0x1064 0x0>;
2776 iommus = <&apps_smmu 0x1005 0x80>,
2777 <&apps_smmu 0x1065 0x0>;
2784 iommus = <&apps_smmu 0x1006 0x80>,
2785 <&apps_smmu 0x1066 0x0>;
2792 iommus = <&apps_smmu 0x1007 0x80>,
2793 <&apps_smmu 0x1067 0x0>;
2804 #size-cells = <0>;
2809 #sound-dai-cells = <0>;
2815 iommus = <&apps_smmu 0x1001 0x80>,
2816 <&apps_smmu 0x1061 0x0>;
2842 reg = <0 0x06aa0000 0 0x1000>;
2849 #clock-cells = <0>;
2856 reg = <0 0x06ab0000 0 0x10000>;
2862 pinctrl-0 = <&wsa2_swr_active>;
2868 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2869 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2870 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2871 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2872 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2873 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2874 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2875 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2876 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2879 #size-cells = <0>;
2886 reg = <0 0x06ac0000 0 0x1000>;
2893 #clock-cells = <0>;
2900 reg = <0 0x06ad0000 0 0x10000>;
2906 pinctrl-0 = <&rx_swr_active>;
2912 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2913 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2914 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2915 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2916 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2917 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2918 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2919 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2920 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2923 #size-cells = <0>;
2930 reg = <0 0x06ae0000 0 0x1000>;
2937 #clock-cells = <0>;
2944 reg = <0 0x06b00000 0 0x1000>;
2951 #clock-cells = <0>;
2958 reg = <0 0x06b10000 0 0x10000>;
2964 pinctrl-0 = <&wsa_swr_active>;
2970 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2971 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2972 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2973 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2974 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2975 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2976 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2977 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2978 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2981 #size-cells = <0>;
2988 reg = <0 0x06d30000 0 0x10000>;
2996 pinctrl-0 = <&tx_swr_active>;
3000 qcom,dout-ports = <0>;
3001 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
3002 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
3003 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
3004 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
3005 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
3006 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
3007 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
3008 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
3009 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
3012 #size-cells = <0>;
3019 reg = <0 0x06d44000 0 0x1000>;
3025 #clock-cells = <0>;
3032 reg = <0 0x06e80000 0 0x20000>,
3033 <0 0x07250000 0 0x10000>;
3036 gpio-ranges = <&lpass_tlmm 0 0 23>;
3149 reg = <0 0x07400000 0 0x19080>;
3156 reg = <0 0x07430000 0 0x3a200>;
3163 reg = <0 0x07e40000 0 0xe080>;
3170 reg = <0 0x08804000 0 0x1000>;
3180 iommus = <&apps_smmu 0x540 0>;
3181 qcom,dll-config = <0x0007642c>;
3182 qcom,ddr-config = <0x80040868>;
3195 sdhci-caps-mask = <0x3 0>;
3227 reg = <0 0x0aa00000 0 0xf0000>;
3259 iommus = <&apps_smmu 0x1940 0>,
3260 <&apps_smmu 0x1947 0>;
3307 reg = <0 0x0aaf0000 0 0x10000>;
3319 reg = <0 0x0ac15000 0 0x1000>;
3328 pinctrl-0 = <&cci0_0_default &cci0_1_default>;
3333 #size-cells = <0>;
3335 cci0_i2c0: i2c-bus@0 {
3336 reg = <0>;
3339 #size-cells = <0>;
3346 #size-cells = <0>;
3352 reg = <0 0x0ac16000 0 0x1000>;
3361 pinctrl-0 = <&cci1_0_default>;
3366 #size-cells = <0>;
3368 cci1_i2c0: i2c-bus@0 {
3369 reg = <0>;
3372 #size-cells = <0>;
3378 reg = <0 0x0ac17000 0 0x1000>;
3387 pinctrl-0 = <&cci2_0_default &cci2_1_default>;
3392 #size-cells = <0>;
3394 cci2_i2c0: i2c-bus@0 {
3395 reg = <0>;
3398 #size-cells = <0>;
3405 #size-cells = <0>;
3412 reg = <0x0 0x0acb7000 0x0 0x0d00>,
3413 <0x0 0x0acb9000 0x0 0x0d00>,
3414 <0x0 0x0acbb000 0x0 0x0d00>,
3415 <0x0 0x0acca000 0x0 0x0a00>,
3416 <0x0 0x0acce000 0x0 0x0a00>,
3417 <0x0 0x0acb6000 0x0 0x1000>,
3418 <0x0 0x0ace4000 0x0 0x2000>,
3419 <0x0 0x0ace6000 0x0 0x2000>,
3420 <0x0 0x0ace8000 0x0 0x2000>,
3421 <0x0 0x0acea000 0x0 0x2000>,
3422 <0x0 0x0acec000 0x0 0x2000>,
3423 <0x0 0x0acee000 0x0 0x2000>,
3424 <0x0 0x0acf0000 0x0 0x2000>,
3425 <0x0 0x0acf2000 0x0 0x2000>,
3426 <0x0 0x0ac62000 0x0 0xf000>,
3427 <0x0 0x0ac71000 0x0 0xf000>,
3428 <0x0 0x0ac80000 0x0 0xf000>,
3429 <0x0 0x0accb000 0x0 0x1800>,
3430 <0x0 0x0accf000 0x0 0x1800>;
3568 iommus = <&apps_smmu 0x800 0x20>;
3583 #size-cells = <0>;
3585 port@0 {
3586 reg = <0>;
3621 reg = <0 0x0ade0000 0 0x20000>;
3635 reg = <0 0x0ae00000 0 0x1000>;
3657 iommus = <&apps_smmu 0x1c00 0x2>;
3667 reg = <0 0x0ae01000 0 0x8f000>,
3668 <0 0x0aeb0000 0 0x3000>;
3672 interrupts = <0>;
3696 #size-cells = <0>;
3698 port@0 {
3699 reg = <0>;
3747 reg = <0 0xae90000 0 0x200>,
3748 <0 0xae90200 0 0x200>,
3749 <0 0xae90400 0 0xc00>,
3750 <0 0xae91000 0 0x400>,
3751 <0 0xae91400 0 0x400>;
3773 #sound-dai-cells = <0>;
3782 #size-cells = <0>;
3784 port@0 {
3785 reg = <0>;
3826 reg = <0 0x0ae94000 0 0x400>;
3858 #size-cells = <0>;
3864 #size-cells = <0>;
3866 port@0 {
3867 reg = <0>;
3902 reg = <0 0x0ae95000 0 0x200>,
3903 <0 0x0ae95200 0 0x280>,
3904 <0 0x0ae95500 0 0x400>;
3914 #phy-cells = <0>;
3921 reg = <0 0x0ae96000 0 0x400>;
3953 #size-cells = <0>;
3959 #size-cells = <0>;
3961 port@0 {
3962 reg = <0>;
3978 reg = <0 0x0ae97000 0 0x200>,
3979 <0 0x0ae97200 0 0x280>,
3980 <0 0x0ae97500 0 0x400>;
3990 #phy-cells = <0>;
3998 reg = <0 0x0af00000 0 0x20000>;
4009 <0>, /* dp1 */
4010 <0>,
4011 <0>, /* dp2 */
4012 <0>,
4013 <0>, /* dp3 */
4014 <0>;
4024 reg = <0x0 0x088e3000 0x0 0x154>;
4025 #phy-cells = <0>;
4037 reg = <0x0 0x088e8000 0x0 0x3000>;
4060 #size-cells = <0>;
4062 port@0 {
4063 reg = <0>;
4089 reg = <0x0 0x0a6f8800 0x0 0x400>;
4137 reg = <0x0 0x0a600000 0x0 0xcd00>;
4139 iommus = <&apps_smmu 0x40 0x0>;
4143 snps,hird-threshold = /bits/ 8 <0x0>;
4159 #size-cells = <0>;
4161 port@0 {
4162 reg = <0>;
4181 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4182 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4192 reg = <0 0x0c271000 0 0x1000>, /* TM */
4193 <0 0x0c222000 0 0x1000>; /* SROT */
4203 reg = <0 0x0c272000 0 0x1000>, /* TM */
4204 <0 0x0c223000 0 0x1000>; /* SROT */
4214 reg = <0 0x0c273000 0 0x1000>, /* TM */
4215 <0 0x0c224000 0 0x1000>; /* SROT */
4225 reg = <0 0x0c300000 0 0x400>;
4231 #clock-cells = <0>;
4236 reg = <0 0x0c3f0000 0 0x400>;
4242 reg = <0 0x0c400000 0 0x3000>,
4243 <0 0x0c500000 0 0x400000>,
4244 <0 0x0c440000 0 0x80000>,
4245 <0 0x0c4c0000 0 0x20000>,
4246 <0 0x0c42d000 0 0x4000>;
4250 qcom,ee = <0>;
4251 qcom,channel = <0>;
4252 qcom,bus-id = <0>;
4254 #size-cells = <0>;
4261 reg = <0 0x0f100000 0 0x300000>;
4267 gpio-ranges = <&tlmm 0 0 211>;
4270 cci0_0_default: cci0-0-default-state {
4286 cci0_0_sleep: cci0-0-sleep-state {
4334 cci1_0_default: cci1-0-default-state {
4350 cci1_0_sleep: cci1-0-sleep-state {
4366 cci2_0_default: cci2-0-default-state {
4382 cci2_0_sleep: cci2-0-sleep-state {
4953 reg = <0 0x15000000 0 0x100000>;
5058 reg = <0 0x17100000 0 0x10000>, /* GICD */
5059 <0 0x17180000 0 0x200000>; /* GICR * 8 */
5064 redistributor-stride = <0 0x40000>;
5071 reg = <0 0x17140000 0 0x20000>;
5079 reg = <0 0x17420000 0 0x1000>;
5080 ranges = <0 0 0 0x20000000>;
5085 reg = <0x17421000 0x1000>,
5086 <0x17422000 0x1000>;
5087 frame-number = <0>;
5093 reg = <0x17423000 0x1000>;
5100 reg = <0x17425000 0x1000>;
5107 reg = <0x17427000 0x1000>;
5114 reg = <0x17429000 0x1000>;
5121 reg = <0x1742b000 0x1000>;
5128 reg = <0x1742d000 0x1000>;
5138 reg = <0 0x17a00000 0 0x10000>,
5139 <0 0x17a10000 0 0x10000>,
5140 <0 0x17a20000 0 0x10000>,
5141 <0 0x17a30000 0 0x10000>;
5142 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
5146 qcom,tcs-offset = <0xd00>;
5149 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5236 reg = <0 0x17d91000 0 0x1000>,
5237 <0 0x17d92000 0 0x1000>,
5238 <0 0x17d93000 0 0x1000>;
5245 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5252 reg = <0 0x24091000 0 0x1000>;
5262 opp-0 {
5302 reg = <0 0x240b6400 0 0x600>;
5312 opp-0 {
5340 reg = <0 0x24100000 0 0xbb800>;
5347 reg = <0 0x25000000 0 0x200000>,
5348 <0 0x25200000 0 0x200000>,
5349 <0 0x25400000 0 0x200000>,
5350 <0 0x25600000 0 0x200000>,
5351 <0 0x25800000 0 0x200000>,
5352 <0 0x25a00000 0 0x200000>;
5364 reg = <0 0x320c0000 0 0xe080>;
5371 reg = <0x0 0x32300000 0x0 0x10000>;
5374 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
5396 qcom,smem-states = <&smp2p_cdsp_out 0>;
5417 #size-cells = <0>;
5422 iommus = <&apps_smmu 0x1961 0x0>,
5423 <&apps_smmu 0x0c01 0x20>,
5424 <&apps_smmu 0x19c1 0x10>;
5431 iommus = <&apps_smmu 0x1962 0x0>,
5432 <&apps_smmu 0x0c02 0x20>,
5433 <&apps_smmu 0x19c2 0x10>;
5440 iommus = <&apps_smmu 0x1963 0x0>,
5441 <&apps_smmu 0x0c03 0x20>,
5442 <&apps_smmu 0x19c3 0x10>;
5449 iommus = <&apps_smmu 0x1964 0x0>,
5450 <&apps_smmu 0x0c04 0x20>,
5451 <&apps_smmu 0x19c4 0x10>;
5458 iommus = <&apps_smmu 0x1965 0x0>,
5459 <&apps_smmu 0x0c05 0x20>,
5460 <&apps_smmu 0x19c5 0x10>;
5467 iommus = <&apps_smmu 0x1966 0x0>,
5468 <&apps_smmu 0x0c06 0x20>,
5469 <&apps_smmu 0x19c6 0x10>;
5476 iommus = <&apps_smmu 0x1967 0x0>,
5477 <&apps_smmu 0x0c07 0x20>,
5478 <&apps_smmu 0x19c7 0x10>;
5485 iommus = <&apps_smmu 0x1968 0x0>,
5486 <&apps_smmu 0x0c08 0x20>,
5487 <&apps_smmu 0x19c8 0x10>;
5499 thermal-sensors = <&tsens0 0>;
5853 thermal-sensors = <&tsens1 0>;
6271 thermal-sensors = <&tsens2 0>;
6288 gpuss-0-thermal {