Lines Matching +full:0 +full:x00884000
81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 cpu0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
131 reg = <0x0 0x100>;
132 clocks = <&cpufreq_hw 0>;
139 qcom,freq-domain = <&cpufreq_hw 0>;
141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
147 cache-size = <0x20000>;
156 reg = <0x0 0x200>;
157 clocks = <&cpufreq_hw 0>;
164 qcom,freq-domain = <&cpufreq_hw 0>;
166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
172 cache-size = <0x20000>;
181 reg = <0x0 0x300>;
182 clocks = <&cpufreq_hw 0>;
189 qcom,freq-domain = <&cpufreq_hw 0>;
191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
197 cache-size = <0x20000>;
206 reg = <0x0 0x400>;
216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
222 cache-size = <0x40000>;
231 reg = <0x0 0x500>;
241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
247 cache-size = <0x40000>;
256 reg = <0x0 0x600>;
266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
272 cache-size = <0x40000>;
281 reg = <0x0 0x700>;
291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
297 cache-size = <0x80000>;
342 little_cpu_sleep_0: cpu-sleep-0-0 {
345 arm,psci-suspend-param = <0x40000004>;
352 big_cpu_sleep_0: cpu-sleep-1-0 {
355 arm,psci-suspend-param = <0x40000004>;
364 cluster_sleep_0: cluster-sleep-0 {
366 arm,psci-suspend-param = <0x4100c244>;
673 qcom,dload-mode = <&tcsr 0x13000>;
681 reg = <0x0 0x80000000 0x0 0x0>;
694 #power-domain-cells = <0>;
700 #power-domain-cells = <0>;
706 #power-domain-cells = <0>;
712 #power-domain-cells = <0>;
718 #power-domain-cells = <0>;
724 #power-domain-cells = <0>;
730 #power-domain-cells = <0>;
736 #power-domain-cells = <0>;
742 #power-domain-cells = <0>;
772 reg = <0x0 0x80000000 0x0 0x600000>;
777 reg = <0x0 0x80700000 0x0 0x160000>;
783 reg = <0x0 0x80860000 0x0 0x20000>;
788 reg = <0x0 0x80900000 0x0 0x200000>;
793 reg = <0x0 0x80b00000 0x0 0x5300000>;
798 reg = <0x0 0x86200000 0x0 0x500000>;
803 reg = <0x0 0x86700000 0x0 0x100000>;
808 reg = <0x0 0x86800000 0x0 0x10000>;
813 reg = <0x0 0x86810000 0x0 0xa000>;
818 reg = <0x0 0x8681a000 0x0 0x2000>;
823 reg = <0x0 0x86900000 0x0 0x500000>;
828 reg = <0x0 0x86e00000 0x0 0x500000>;
833 reg = <0x0 0x87300000 0x0 0x500000>;
838 reg = <0x0 0x87800000 0x0 0x1400000>;
843 reg = <0x0 0x88c00000 0x0 0x1500000>;
848 reg = <0x0 0x8a100000 0x0 0x1d00000>;
853 reg = <0x0 0x8be00000 0x0 0x100000>;
858 reg = <0x0 0x8bf00000 0x0 0x4600000>;
878 qcom,local-pid = <0>;
902 qcom,local-pid = <0>;
926 qcom,local-pid = <0>;
941 soc: soc@0 {
944 ranges = <0 0 0 0 0x10 0>;
945 dma-ranges = <0 0 0 0 0x10 0>;
950 reg = <0x0 0x00100000 0x0 0x1f0000>;
964 reg = <0 0x00408000 0 0x1000>;
973 reg = <0 0x00784000 0 0x8ff>;
978 reg = <0x19b 0x1>;
985 reg = <0 0x00793000 0 0x1000>;
992 reg = <0 0x00800000 0 0x70000>;
1004 dma-channel-mask = <0x3f>;
1005 iommus = <&apps_smmu 0x76 0x0>;
1012 reg = <0x0 0x008c0000 0x0 0x6000>;
1018 iommus = <&apps_smmu 0x63 0x0>;
1024 reg = <0 0x00880000 0 0x4000>;
1028 pinctrl-0 = <&qup_i2c14_default>;
1030 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1031 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1034 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1036 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1041 #size-cells = <0>;
1047 reg = <0 0x00880000 0 0x4000>;
1051 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1052 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1056 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1057 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1058 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1063 #size-cells = <0>;
1069 reg = <0 0x00884000 0 0x4000>;
1073 pinctrl-0 = <&qup_i2c15_default>;
1075 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1079 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1081 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1086 #size-cells = <0>;
1092 reg = <0 0x00884000 0 0x4000>;
1096 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1101 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1108 #size-cells = <0>;
1114 reg = <0 0x00888000 0 0x4000>;
1118 pinctrl-0 = <&qup_i2c16_default>;
1120 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1124 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1125 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1131 #size-cells = <0>;
1137 reg = <0 0x00888000 0 0x4000>;
1141 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1146 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1153 #size-cells = <0>;
1159 reg = <0 0x0088c000 0 0x4000>;
1163 pinctrl-0 = <&qup_i2c17_default>;
1165 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1169 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1171 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1176 #size-cells = <0>;
1182 reg = <0 0x0088c000 0 0x4000>;
1186 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1191 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1192 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1193 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1198 #size-cells = <0>;
1204 reg = <0 0x0088c000 0 0x4000>;
1208 pinctrl-0 = <&qup_uart17_default>;
1212 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1221 reg = <0 0x00890000 0 0x4000>;
1225 pinctrl-0 = <&qup_i2c18_default>;
1227 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1231 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1232 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1233 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1238 #size-cells = <0>;
1244 reg = <0 0x00890000 0 0x4000>;
1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1253 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1255 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1260 #size-cells = <0>;
1266 reg = <0 0x00890000 0 0x4000>;
1270 pinctrl-0 = <&qup_uart18_default>;
1274 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1275 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1283 reg = <0 0x00894000 0 0x4000>;
1287 pinctrl-0 = <&qup_i2c19_default>;
1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1293 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1295 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1300 #size-cells = <0>;
1306 reg = <0 0x00894000 0 0x4000>;
1310 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1315 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1316 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1317 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1322 #size-cells = <0>;
1329 reg = <0 0x00900000 0 0x70000>;
1344 dma-channel-mask = <0x7ff>;
1345 iommus = <&apps_smmu 0x5b6 0x0>;
1352 reg = <0x0 0x009c0000 0x0 0x6000>;
1358 iommus = <&apps_smmu 0x5a3 0x0>;
1364 reg = <0 0x00980000 0 0x4000>;
1368 pinctrl-0 = <&qup_i2c0_default>;
1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1371 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1374 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1381 #size-cells = <0>;
1387 reg = <0 0x00980000 0 0x4000>;
1391 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1392 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1396 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1397 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1398 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1403 #size-cells = <0>;
1409 reg = <0 0x00984000 0 0x4000>;
1413 pinctrl-0 = <&qup_i2c1_default>;
1415 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1419 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1421 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1426 #size-cells = <0>;
1432 reg = <0 0x00984000 0 0x4000>;
1436 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1441 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1442 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1443 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1448 #size-cells = <0>;
1454 reg = <0 0x00988000 0 0x4000>;
1458 pinctrl-0 = <&qup_i2c2_default>;
1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1464 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1466 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1471 #size-cells = <0>;
1477 reg = <0 0x00988000 0 0x4000>;
1481 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1486 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1488 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1493 #size-cells = <0>;
1499 reg = <0 0x00988000 0 0x4000>;
1503 pinctrl-0 = <&qup_uart2_default>;
1507 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1508 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1516 reg = <0 0x0098c000 0 0x4000>;
1520 pinctrl-0 = <&qup_i2c3_default>;
1522 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1526 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1528 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1533 #size-cells = <0>;
1539 reg = <0 0x0098c000 0 0x4000>;
1543 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1548 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1549 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1550 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1555 #size-cells = <0>;
1561 reg = <0 0x00990000 0 0x4000>;
1565 pinctrl-0 = <&qup_i2c4_default>;
1567 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1571 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1572 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1573 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1578 #size-cells = <0>;
1584 reg = <0 0x00990000 0 0x4000>;
1588 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1593 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1595 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1600 #size-cells = <0>;
1606 reg = <0 0x00994000 0 0x4000>;
1610 pinctrl-0 = <&qup_i2c5_default>;
1612 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1616 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1618 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1623 #size-cells = <0>;
1629 reg = <0 0x00994000 0 0x4000>;
1633 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1638 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1640 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1645 #size-cells = <0>;
1651 reg = <0 0x00998000 0 0x4000>;
1655 pinctrl-0 = <&qup_i2c6_default>;
1657 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1661 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1663 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1668 #size-cells = <0>;
1674 reg = <0 0x00998000 0 0x4000>;
1678 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1683 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1685 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1690 #size-cells = <0>;
1696 reg = <0 0x00998000 0 0x4000>;
1700 pinctrl-0 = <&qup_uart6_default>;
1704 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1705 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1713 reg = <0 0x0099c000 0 0x4000>;
1717 pinctrl-0 = <&qup_i2c7_default>;
1719 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1723 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1725 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1730 #size-cells = <0>;
1736 reg = <0 0x0099c000 0 0x4000>;
1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1745 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1746 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1747 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1752 #size-cells = <0>;
1759 reg = <0 0x00a00000 0 0x70000>;
1771 dma-channel-mask = <0x3f>;
1772 iommus = <&apps_smmu 0x56 0x0>;
1779 reg = <0x0 0x00ac0000 0x0 0x6000>;
1785 iommus = <&apps_smmu 0x43 0x0>;
1791 reg = <0 0x00a80000 0 0x4000>;
1795 pinctrl-0 = <&qup_i2c8_default>;
1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1798 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1801 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1803 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1808 #size-cells = <0>;
1814 reg = <0 0x00a80000 0 0x4000>;
1818 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1819 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1823 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1825 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1830 #size-cells = <0>;
1836 reg = <0 0x00a84000 0 0x4000>;
1840 pinctrl-0 = <&qup_i2c9_default>;
1842 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1846 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1848 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1853 #size-cells = <0>;
1859 reg = <0 0x00a84000 0 0x4000>;
1863 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1868 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1870 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1875 #size-cells = <0>;
1881 reg = <0 0x00a88000 0 0x4000>;
1885 pinctrl-0 = <&qup_i2c10_default>;
1887 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1891 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1898 #size-cells = <0>;
1904 reg = <0 0x00a88000 0 0x4000>;
1908 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1920 #size-cells = <0>;
1926 reg = <0 0x00a8c000 0 0x4000>;
1930 pinctrl-0 = <&qup_i2c11_default>;
1932 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1936 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1943 #size-cells = <0>;
1949 reg = <0 0x00a8c000 0 0x4000>;
1953 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1958 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1965 #size-cells = <0>;
1971 reg = <0 0x00a90000 0 0x4000>;
1975 pinctrl-0 = <&qup_i2c12_default>;
1977 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1981 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1983 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1988 #size-cells = <0>;
1994 reg = <0 0x00a90000 0 0x4000>;
1998 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2003 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2004 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2005 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2010 #size-cells = <0>;
2016 reg = <0x0 0x00a90000 0x0 0x4000>;
2020 pinctrl-0 = <&qup_uart12_default>;
2024 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2033 reg = <0 0x00a94000 0 0x4000>;
2037 pinctrl-0 = <&qup_i2c13_default>;
2039 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2043 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2045 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2050 #size-cells = <0>;
2056 reg = <0 0x00a94000 0 0x4000>;
2060 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2065 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2067 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2072 #size-cells = <0>;
2079 reg = <0 0x01500000 0 0xa580>;
2086 reg = <0 0x01620000 0 0x1c200>;
2093 reg = <0 0x0163d000 0 0x1000>;
2100 reg = <0 0x016e0000 0 0x1f180>;
2107 reg = <0 0x01700000 0 0x33000>;
2114 reg = <0 0x01733000 0 0xa180>;
2121 reg = <0 0x01740000 0 0x1f080>;
2128 reg = <0 0x01c00000 0 0x3000>,
2129 <0 0x60000000 0 0xf1d>,
2130 <0 0x60000f20 0 0xa8>,
2131 <0 0x60001000 0 0x1000>,
2132 <0 0x60100000 0 0x100000>,
2133 <0 0x01c03000 0 0x1000>;
2136 linux,pci-domain = <0>;
2137 bus-range = <0x00 0xff>;
2143 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2144 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2165 interrupt-map-mask = <0 0 0 0x7>;
2166 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2167 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2168 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2169 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2188 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2189 <0x100 &apps_smmu 0x1c01 0x1>;
2203 pinctrl-0 = <&pcie0_default_state>;
2208 pcieport0: pcie@0 {
2210 reg = <0x0 0x0 0x0 0x0 0x0>;
2211 bus-range = <0x01 0xff>;
2221 reg = <0 0x01c06000 0 0x1000>;
2235 #clock-cells = <0>;
2237 #phy-cells = <0>;
2250 reg = <0 0x01c08000 0 0x3000>,
2251 <0 0x40000000 0 0xf1d>,
2252 <0 0x40000f20 0 0xa8>,
2253 <0 0x40001000 0 0x1000>,
2254 <0 0x40100000 0 0x100000>,
2255 <0 0x01c0b000 0 0x1000>;
2259 bus-range = <0x00 0xff>;
2265 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2266 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2287 interrupt-map-mask = <0 0 0 0x7>;
2288 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2289 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2290 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2291 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2315 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2316 <0x100 &apps_smmu 0x1c81 0x1>;
2330 pinctrl-0 = <&pcie1_default_state>;
2335 pcie@0 {
2337 reg = <0x0 0x0 0x0 0x0 0x0>;
2338 bus-range = <0x01 0xff>;
2348 reg = <0 0x01c0e000 0 0x1000>;
2362 #clock-cells = <0>;
2364 #phy-cells = <0>;
2377 reg = <0 0x01c10000 0 0x3000>,
2378 <0 0x64000000 0 0xf1d>,
2379 <0 0x64000f20 0 0xa8>,
2380 <0 0x64001000 0 0x1000>,
2381 <0 0x64100000 0 0x100000>,
2382 <0 0x01c13000 0 0x1000>;
2386 bus-range = <0x00 0xff>;
2392 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2393 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2414 interrupt-map-mask = <0 0 0 0x7>;
2415 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2416 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2417 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2418 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2442 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2443 <0x100 &apps_smmu 0x1d01 0x1>;
2457 pinctrl-0 = <&pcie2_default_state>;
2462 pcie@0 {
2464 reg = <0x0 0x0 0x0 0x0 0x0>;
2465 bus-range = <0x01 0xff>;
2475 reg = <0 0x01c16000 0 0x1000>;
2489 #clock-cells = <0>;
2491 #phy-cells = <0>;
2505 reg = <0 0x01d84000 0 0x3000>;
2516 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2539 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2540 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2550 /bits/ 64 <0>,
2551 /bits/ 64 <0>,
2553 /bits/ 64 <0>,
2554 /bits/ 64 <0>,
2555 /bits/ 64 <0>,
2556 /bits/ 64 <0>;
2562 /bits/ 64 <0>,
2563 /bits/ 64 <0>,
2565 /bits/ 64 <0>,
2566 /bits/ 64 <0>,
2567 /bits/ 64 <0>,
2568 /bits/ 64 <0>;
2576 reg = <0 0x01d87000 0 0x1000>;
2585 resets = <&ufs_mem_hc 0>;
2590 #phy-cells = <0>;
2597 reg = <0 0x01dc4000 0 0x24000>;
2600 qcom,ee = <0>;
2604 iommus = <&apps_smmu 0x592 0x0000>,
2605 <&apps_smmu 0x598 0x0000>,
2606 <&apps_smmu 0x599 0x0000>,
2607 <&apps_smmu 0x59f 0x0000>,
2608 <&apps_smmu 0x586 0x0011>,
2609 <&apps_smmu 0x596 0x0011>;
2614 reg = <0 0x01dfa000 0 0x6000>;
2617 iommus = <&apps_smmu 0x592 0x0000>,
2618 <&apps_smmu 0x598 0x0000>,
2619 <&apps_smmu 0x599 0x0000>,
2620 <&apps_smmu 0x59f 0x0000>,
2621 <&apps_smmu 0x586 0x0011>,
2622 <&apps_smmu 0x596 0x0011>;
2623 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2629 reg = <0x0 0x01f40000 0x0 0x40000>;
2635 reg = <0x0 0x1fc0000 0x0 0x30000>;
2640 reg = <0 0x03240000 0 0x1000>;
2649 #clock-cells = <0>;
2654 pinctrl-0 = <&wsa_swr_active>;
2660 reg = <0 0x03250000 0 0x2000>;
2669 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2670 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2671 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2672 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2676 #size-cells = <0>;
2683 reg = <0 0x03370000 0 0x1000>;
2690 #clock-cells = <0>;
2697 pinctrl-0 = <&rx_swr_active>;
2699 reg = <0 0x03200000 0 0x1000>;
2710 #clock-cells = <0>;
2716 reg = <0 0x03210000 0 0x2000>;
2723 qcom,din-ports = <0>;
2726 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2727 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2728 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2729 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2730 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2731 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2732 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2733 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2734 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2738 #size-cells = <0>;
2743 pinctrl-0 = <&tx_swr_active>;
2745 reg = <0 0x03220000 0 0x1000>;
2756 #clock-cells = <0>;
2763 reg = <0 0x03230000 0 0x2000>;
2774 qcom,dout-ports = <0>;
2775 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2776 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2777 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2778 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2779 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2780 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2781 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2782 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2783 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2786 #size-cells = <0>;
2791 reg = <0 0x033c0000 0x0 0x20000>,
2792 <0 0x03550000 0x0 0x10000>;
2795 gpio-ranges = <&lpass_tlmm 0 0 14>;
2930 reg = <0 0x03d00000 0 0x40000>;
2935 iommus = <&adreno_smmu 0 0x401>;
2957 opp-supported-hw = <0xa>;
2963 opp-supported-hw = <0xb>;
2969 opp-supported-hw = <0xf>;
2975 opp-supported-hw = <0xf>;
2981 opp-supported-hw = <0xf>;
2987 opp-supported-hw = <0xf>;
2993 opp-supported-hw = <0xf>;
3001 reg = <0 0x03d6a000 0 0x30000>,
3002 <0 0x3de0000 0 0x10000>,
3003 <0 0xb290000 0 0x10000>,
3004 <0 0xb490000 0 0x10000>;
3022 iommus = <&adreno_smmu 5 0x400>;
3040 reg = <0 0x03d90000 0 0x9000>;
3055 reg = <0 0x03da0000 0 0x10000>;
3079 reg = <0 0x05c00000 0 0x4000>;
3082 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3100 qcom,smem-states = <&smp2p_slpi_out 0>;
3121 #size-cells = <0>;
3126 iommus = <&apps_smmu 0x0541 0x0>;
3132 iommus = <&apps_smmu 0x0542 0x0>;
3138 iommus = <&apps_smmu 0x0543 0x0>;
3147 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3164 reg = <0 0x06004000 0 0x1000>;
3180 #size-cells = <0>;
3200 reg = <0 0x06005000 0 0x1000>;
3224 reg = <0 0x06041000 0 0x1000>;
3239 #size-cells = <0>;
3259 reg = <0 0x06042000 0 0x1000>;
3274 #size-cells = <0>;
3287 reg = <0 0x06045000 0 0x1000>;
3302 #size-cells = <0>;
3304 port@0 {
3305 reg = <0>;
3322 reg = <0 0x06046000 0 0x1000>;
3346 reg = <0 0x06048000 0 0x1000>;
3363 reg = <0 0x0684c000 0 0x1000>;
3379 arm,primecell-periphid = <0x000bb908>;
3381 reg = <0 0x06b04000 0 0x1000>;
3396 #size-cells = <0>;
3409 reg = <0 0x06b05000 0 0x1000>;
3434 reg = <0 0x06b06000 0 0x1000>;
3458 reg = <0 0x06c08000 0 0x1000>;
3474 reg = <0 0x06c0b000 0 0x1000>;
3489 #size-cells = <0>;
3502 reg = <0 0x06c2d000 0 0x1000>;
3517 #size-cells = <0>;
3530 reg = <0 0x07040000 0 0x1000>;
3549 reg = <0 0x07140000 0 0x1000>;
3568 reg = <0 0x07240000 0 0x1000>;
3587 reg = <0 0x07340000 0 0x1000>;
3606 reg = <0 0x07440000 0 0x1000>;
3625 reg = <0 0x07540000 0 0x1000>;
3644 reg = <0 0x07640000 0 0x1000>;
3663 reg = <0 0x07740000 0 0x1000>;
3682 reg = <0 0x07800000 0 0x1000>;
3697 #size-cells = <0>;
3699 port@0 {
3700 reg = <0>;
3759 reg = <0 0x07810000 0 0x1000>;
3783 reg = <0 0x08300000 0 0x10000>;
3786 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3802 qcom,smem-states = <&smp2p_cdsp_out 0>;
3823 #size-cells = <0>;
3828 iommus = <&apps_smmu 0x1001 0x0460>;
3834 iommus = <&apps_smmu 0x1002 0x0460>;
3840 iommus = <&apps_smmu 0x1003 0x0460>;
3846 iommus = <&apps_smmu 0x1004 0x0460>;
3852 iommus = <&apps_smmu 0x1005 0x0460>;
3858 iommus = <&apps_smmu 0x1006 0x0460>;
3864 iommus = <&apps_smmu 0x1007 0x0460>;
3870 iommus = <&apps_smmu 0x1008 0x0460>;
3881 reg = <0 0x088e3000 0 0x400>;
3883 #phy-cells = <0>;
3894 reg = <0 0x088e4000 0 0x400>;
3896 #phy-cells = <0>;
3906 reg = <0 0x088e8000 0 0x3000>;
3929 #size-cells = <0>;
3931 port@0 {
3932 reg = <0>;
3954 reg = <0 0x088eb000 0 0x1000>;
3965 #clock-cells = <0>;
3966 #phy-cells = <0>;
3978 reg = <0 0x08804000 0 0x1000>;
3988 iommus = <&apps_smmu 0x4a0 0x0>;
3989 qcom,dll-config = <0x0007642c>;
3990 qcom,ddr-config = <0x80040868>;
4023 reg = <0 0x09091000 0 0x1000>;
4085 reg = <0 0x090b6400 0 0x600>;
4145 reg = <0 0x090c0000 0 0x4200>;
4152 reg = <0 0x09100000 0 0xb4000>;
4159 reg = <0 0x09990000 0 0x1600>;
4166 reg = <0 0x0a6f8800 0 0x400>;
4206 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4207 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4212 reg = <0 0x0a600000 0 0xcd00>;
4214 iommus = <&apps_smmu 0x0 0x0>;
4224 #size-cells = <0>;
4226 port@0 {
4227 reg = <0>;
4246 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4247 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4248 <0 0x09600000 0 0x50000>;
4255 reg = <0 0x0a8f8800 0 0x400>;
4295 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4296 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4301 reg = <0 0x0a800000 0 0xcd00>;
4303 iommus = <&apps_smmu 0x20 0>;
4315 reg = <0 0x0aa00000 0 0x100000>;
4328 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4329 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4332 iommus = <&apps_smmu 0x2100 0x0400>;
4376 reg = <0 0x0abf0000 0 0x10000>;
4391 #size-cells = <0>;
4393 reg = <0 0x0ac4f000 0 0x1000>;
4408 pinctrl-0 = <&cci0_default>;
4414 cci0_i2c0: i2c-bus@0 {
4415 reg = <0>;
4418 #size-cells = <0>;
4425 #size-cells = <0>;
4432 #size-cells = <0>;
4434 reg = <0 0x0ac50000 0 0x1000>;
4449 pinctrl-0 = <&cci1_default>;
4455 cci1_i2c0: i2c-bus@0 {
4456 reg = <0>;
4459 #size-cells = <0>;
4466 #size-cells = <0>;
4474 reg = <0 0x0ac6a000 0 0x2000>,
4475 <0 0x0ac6c000 0 0x2000>,
4476 <0 0x0ac6e000 0 0x1000>,
4477 <0 0x0ac70000 0 0x1000>,
4478 <0 0x0ac72000 0 0x1000>,
4479 <0 0x0ac74000 0 0x1000>,
4480 <0 0x0acb4000 0 0xd000>,
4481 <0 0x0acc3000 0 0xd000>,
4482 <0 0x0acd9000 0 0x2200>,
4483 <0 0x0acdb200 0 0x2200>;
4604 iommus = <&apps_smmu 0x800 0x400>,
4605 <&apps_smmu 0x801 0x400>,
4606 <&apps_smmu 0x840 0x400>,
4607 <&apps_smmu 0x841 0x400>,
4608 <&apps_smmu 0xc00 0x400>,
4609 <&apps_smmu 0xc01 0x400>,
4610 <&apps_smmu 0xc40 0x400>,
4611 <&apps_smmu 0xc41 0x400>;
4613 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4614 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4615 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4616 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4624 #size-cells = <0>;
4626 port@0 {
4627 reg = <0>;
4654 reg = <0 0x0ad00000 0 0x10000>;
4669 reg = <0 0x0ae00000 0 0x1000>;
4672 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4673 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4688 iommus = <&apps_smmu 0x820 0x402>;
4698 reg = <0 0x0ae01000 0 0x8f000>,
4699 <0 0x0aeb0000 0 0x3000>;
4715 interrupts = <0>;
4719 #size-cells = <0>;
4721 port@0 {
4722 reg = <0>;
4771 reg = <0 0xae90000 0 0x200>,
4772 <0 0xae90200 0 0x200>,
4773 <0 0xae90400 0 0x600>,
4774 <0 0xae91000 0 0x400>,
4775 <0 0xae91400 0 0x400>;
4797 #sound-dai-cells = <0>;
4806 #size-cells = <0>;
4808 port@0 {
4809 reg = <0>;
4851 reg = <0 0x0ae94000 0 0x400>;
4883 #size-cells = <0>;
4887 #size-cells = <0>;
4889 port@0 {
4890 reg = <0>;
4925 reg = <0 0x0ae94400 0 0x200>,
4926 <0 0x0ae94600 0 0x280>,
4927 <0 0x0ae94900 0 0x260>;
4933 #phy-cells = <0>;
4945 reg = <0 0x0ae96000 0 0x400>;
4977 #size-cells = <0>;
4981 #size-cells = <0>;
4983 port@0 {
4984 reg = <0>;
5000 reg = <0 0x0ae96400 0 0x200>,
5001 <0 0x0ae96600 0 0x280>,
5002 <0 0x0ae96900 0 0x260>;
5008 #phy-cells = <0>;
5020 reg = <0 0x0af00000 0 0x10000>;
5044 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5045 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5054 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5055 <0 0x0c222000 0 0x1ff>; /* SROT */
5065 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5066 <0 0x0c223000 0 0x1ff>; /* SROT */
5076 reg = <0 0x0c300000 0 0x400>;
5083 #clock-cells = <0>;
5088 reg = <0 0x0c3f0000 0 0x400>;
5093 reg = <0x0 0x0c440000 0x0 0x0001100>,
5094 <0x0 0x0c600000 0x0 0x2000000>,
5095 <0x0 0x0e600000 0x0 0x0100000>,
5096 <0x0 0x0e700000 0x0 0x00a0000>,
5097 <0x0 0x0c40a000 0x0 0x0026000>;
5101 qcom,ee = <0>;
5102 qcom,channel = <0>;
5104 #size-cells = <0>;
5111 reg = <0 0x0f100000 0 0x300000>,
5112 <0 0x0f500000 0 0x300000>,
5113 <0 0x0f900000 0 0x300000>;
5120 gpio-ranges = <&tlmm 0 0 181>;
5868 reg = <0 0x15000000 0 0x100000>;
5974 reg = <0 0x17300000 0 0x100>;
5977 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5995 qcom,smem-states = <&smp2p_adsp_out 0>;
6015 #size-cells = <0>;
6030 #size-cells = <0>;
6047 #size-cells = <0>;
6049 iommus = <&apps_smmu 0x1801 0x0>;
6059 #sound-dai-cells = <0>;
6070 #size-cells = <0>;
6075 iommus = <&apps_smmu 0x1803 0x0>;
6081 iommus = <&apps_smmu 0x1804 0x0>;
6087 iommus = <&apps_smmu 0x1805 0x0>;
6097 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6098 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6104 reg = <0 0x17c10000 0 0x1000>;
6106 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6112 ranges = <0 0 0 0x20000000>;
6114 reg = <0x0 0x17c20000 0x0 0x1000>;
6118 frame-number = <0>;
6121 reg = <0x17c21000 0x1000>,
6122 <0x17c22000 0x1000>;
6128 reg = <0x17c23000 0x1000>;
6135 reg = <0x17c25000 0x1000>;
6142 reg = <0x17c27000 0x1000>;
6149 reg = <0x17c29000 0x1000>;
6156 reg = <0x17c2b000 0x1000>;
6163 reg = <0x17c2d000 0x1000>;
6171 reg = <0x0 0x18200000 0x0 0x10000>,
6172 <0x0 0x18210000 0x0 0x10000>,
6173 <0x0 0x18220000 0x0 0x10000>;
6174 reg-names = "drv-0", "drv-1", "drv-2";
6178 qcom,tcs-offset = <0xd00>;
6248 reg = <0 0x18590000 0 0x1000>;
6258 reg = <0 0x18591000 0 0x1000>,
6259 <0 0x18592000 0 0x1000>,
6260 <0 0x18593000 0 0x1000>;
6269 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6810 thermal-sensors = <&tsens0 0>;
6895 thermal-sensors = <&tsens1 0>;