Lines Matching +full:0 +full:x00884000
35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
92 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
108 reg = <0x0 0x200>;
109 clocks = <&cpufreq_hw 0>;
114 qcom,freq-domain = <&cpufreq_hw 0>;
116 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
132 reg = <0x0 0x300>;
133 clocks = <&cpufreq_hw 0>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
156 reg = <0x0 0x400>;
164 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
180 reg = <0x0 0x500>;
188 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
204 reg = <0x0 0x600>;
212 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
228 reg = <0x0 0x700>;
236 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
288 little_cpu_sleep_0: cpu-sleep-0-0 {
291 arm,psci-suspend-param = <0x40000004>;
298 big_cpu_sleep_0: cpu-sleep-1-0 {
301 arm,psci-suspend-param = <0x40000004>;
310 cluster_sleep_0: cluster-sleep-0 {
312 arm,psci-suspend-param = <0x4100c244>;
620 reg = <0x0 0x80000000 0x0 0x0>;
633 #power-domain-cells = <0>;
639 #power-domain-cells = <0>;
645 #power-domain-cells = <0>;
651 #power-domain-cells = <0>;
657 #power-domain-cells = <0>;
663 #power-domain-cells = <0>;
669 #power-domain-cells = <0>;
675 #power-domain-cells = <0>;
681 #power-domain-cells = <0>;
692 reg = <0x0 0x85700000 0x0 0x600000>;
697 reg = <0x0 0x85d00000 0x0 0x140000>;
702 reg = <0x0 0x85f00000 0x0 0x20000>;
708 reg = <0x0 0x85f20000 0x0 0x20000>;
713 reg = <0x0 0x86000000 0x0 0x200000>;
718 reg = <0x0 0x86200000 0x0 0x3900000>;
724 reg = <0x0 0x89b00000 0x0 0x200000>;
732 reg = <0x0 0x8b700000 0x0 0x500000>;
737 reg = <0x0 0x8bc00000 0x0 0x180000>;
742 reg = <0x0 0x8bd80000 0x0 0x80000>;
747 reg = <0x0 0x8be00000 0x0 0x1a00000>;
752 reg = <0x0 0x8d800000 0x0 0x9600000>;
757 reg = <0x0 0x96e00000 0x0 0x500000>;
762 reg = <0x0 0x97300000 0x0 0x1400000>;
767 reg = <0x0 0x98700000 0x0 0x10000>;
772 reg = <0x0 0x98710000 0x0 0x5000>;
777 reg = <0x0 0x98715000 0x0 0x2000>;
782 reg = <0x0 0x98800000 0x0 0x100000>;
787 reg = <0x0 0x98900000 0x0 0x1400000>;
792 reg = <0x0 0x9e400000 0x0 0x1400000>;
811 qcom,local-pid = <0>;
835 qcom,local-pid = <0>;
859 qcom,local-pid = <0>;
883 qcom,local-pid = <0>;
899 soc: soc@0 {
902 ranges = <0 0 0 0 0x10 0>;
903 dma-ranges = <0 0 0 0 0x10 0>;
908 reg = <0x0 0x00100000 0x0 0x1f0000>;
920 reg = <0 0x00800000 0 0x60000>;
935 dma-channel-mask = <0xfa>;
936 iommus = <&apps_smmu 0x00d6 0x0>;
943 reg = <0x0 0x00020000 0x0 0x10000>,
944 <0x0 0x00036000 0x0 0x100>;
958 iommus = <&apps_smmu 0x3c0 0x0>;
969 reg = <0 0x00784000 0 0x8ff>;
974 reg = <0x133 0x1>;
981 reg = <0x0 0x008c0000 0x0 0x6000>;
985 iommus = <&apps_smmu 0xc3 0x0>;
993 reg = <0 0x00880000 0 0x4000>;
996 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
997 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1000 pinctrl-0 = <&qup_i2c0_default>;
1003 #size-cells = <0>;
1009 reg = <0 0x00880000 0 0x4000>;
1013 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1014 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1017 pinctrl-0 = <&qup_spi0_default>;
1021 #size-cells = <0>;
1027 reg = <0 0x00884000 0 0x4000>;
1030 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1034 pinctrl-0 = <&qup_i2c1_default>;
1037 #size-cells = <0>;
1043 reg = <0 0x00884000 0 0x4000>;
1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1051 pinctrl-0 = <&qup_spi1_default>;
1055 #size-cells = <0>;
1061 reg = <0 0x00888000 0 0x4000>;
1064 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1068 pinctrl-0 = <&qup_i2c2_default>;
1071 #size-cells = <0>;
1077 reg = <0 0x00888000 0 0x4000>;
1081 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1085 pinctrl-0 = <&qup_spi2_default>;
1089 #size-cells = <0>;
1095 reg = <0 0x0088c000 0 0x4000>;
1098 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1102 pinctrl-0 = <&qup_i2c3_default>;
1105 #size-cells = <0>;
1111 reg = <0 0x0088c000 0 0x4000>;
1115 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1119 pinctrl-0 = <&qup_spi3_default>;
1123 #size-cells = <0>;
1129 reg = <0 0x00890000 0 0x4000>;
1132 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1136 pinctrl-0 = <&qup_i2c4_default>;
1139 #size-cells = <0>;
1145 reg = <0 0x00890000 0 0x4000>;
1149 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1153 pinctrl-0 = <&qup_spi4_default>;
1157 #size-cells = <0>;
1163 reg = <0 0x00894000 0 0x4000>;
1166 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1170 pinctrl-0 = <&qup_i2c5_default>;
1173 #size-cells = <0>;
1179 reg = <0 0x00894000 0 0x4000>;
1183 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1187 pinctrl-0 = <&qup_spi5_default>;
1191 #size-cells = <0>;
1197 reg = <0 0x00898000 0 0x4000>;
1200 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1204 pinctrl-0 = <&qup_i2c6_default>;
1207 #size-cells = <0>;
1213 reg = <0 0x00898000 0 0x4000>;
1217 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1221 pinctrl-0 = <&qup_spi6_default>;
1225 #size-cells = <0>;
1231 reg = <0 0x0089c000 0 0x4000>;
1234 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1238 pinctrl-0 = <&qup_i2c7_default>;
1241 #size-cells = <0>;
1247 reg = <0 0x0089c000 0 0x4000>;
1251 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1255 pinctrl-0 = <&qup_spi7_default>;
1259 #size-cells = <0>;
1266 reg = <0 0x00a00000 0 0x60000>;
1281 dma-channel-mask = <0xfa>;
1282 iommus = <&apps_smmu 0x0616 0x0>;
1289 reg = <0x0 0x00ac0000 0x0 0x6000>;
1293 iommus = <&apps_smmu 0x603 0x0>;
1301 reg = <0 0x00a80000 0 0x4000>;
1304 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1305 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1308 pinctrl-0 = <&qup_i2c8_default>;
1311 #size-cells = <0>;
1317 reg = <0 0x00a80000 0 0x4000>;
1321 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1322 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1325 pinctrl-0 = <&qup_spi8_default>;
1329 #size-cells = <0>;
1335 reg = <0 0x00a84000 0 0x4000>;
1338 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1342 pinctrl-0 = <&qup_i2c9_default>;
1345 #size-cells = <0>;
1351 reg = <0 0x00a84000 0 0x4000>;
1355 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1359 pinctrl-0 = <&qup_spi9_default>;
1363 #size-cells = <0>;
1369 reg = <0x0 0x00a84000 0x0 0x4000>;
1372 pinctrl-0 = <&qup_uart9_default>;
1380 reg = <0 0x00a88000 0 0x4000>;
1383 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1387 pinctrl-0 = <&qup_i2c10_default>;
1390 #size-cells = <0>;
1396 reg = <0 0x00a88000 0 0x4000>;
1400 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1404 pinctrl-0 = <&qup_spi10_default>;
1408 #size-cells = <0>;
1414 reg = <0 0x00a8c000 0 0x4000>;
1417 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1421 pinctrl-0 = <&qup_i2c11_default>;
1424 #size-cells = <0>;
1430 reg = <0 0x00a8c000 0 0x4000>;
1434 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1438 pinctrl-0 = <&qup_spi11_default>;
1442 #size-cells = <0>;
1448 reg = <0x0 0x00a90000 0x0 0x4000>;
1457 reg = <0 0x00a90000 0 0x4000>;
1460 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1464 pinctrl-0 = <&qup_i2c12_default>;
1467 #size-cells = <0>;
1473 reg = <0 0x00a90000 0 0x4000>;
1477 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1481 pinctrl-0 = <&qup_spi12_default>;
1485 #size-cells = <0>;
1491 reg = <0 0x00094000 0 0x4000>;
1494 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1498 pinctrl-0 = <&qup_i2c16_default>;
1501 #size-cells = <0>;
1507 reg = <0 0x00a94000 0 0x4000>;
1511 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1515 pinctrl-0 = <&qup_spi16_default>;
1519 #size-cells = <0>;
1526 reg = <0 0x00c00000 0 0x60000>;
1541 dma-channel-mask = <0xfa>;
1542 iommus = <&apps_smmu 0x07b6 0x0>;
1549 reg = <0x0 0x00cc0000 0x0 0x6000>;
1554 iommus = <&apps_smmu 0x7a3 0x0>;
1562 reg = <0 0x00c80000 0 0x4000>;
1565 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1566 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1569 pinctrl-0 = <&qup_i2c17_default>;
1572 #size-cells = <0>;
1578 reg = <0 0x00c80000 0 0x4000>;
1582 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1583 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1586 pinctrl-0 = <&qup_spi17_default>;
1590 #size-cells = <0>;
1596 reg = <0 0x00c84000 0 0x4000>;
1599 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1603 pinctrl-0 = <&qup_i2c18_default>;
1606 #size-cells = <0>;
1612 reg = <0 0x00c84000 0 0x4000>;
1616 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1620 pinctrl-0 = <&qup_spi18_default>;
1624 #size-cells = <0>;
1630 reg = <0 0x00c88000 0 0x4000>;
1633 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1637 pinctrl-0 = <&qup_i2c19_default>;
1640 #size-cells = <0>;
1646 reg = <0 0x00c88000 0 0x4000>;
1650 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1654 pinctrl-0 = <&qup_spi19_default>;
1658 #size-cells = <0>;
1664 reg = <0 0x00c8c000 0 0x4000>;
1667 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1671 pinctrl-0 = <&qup_i2c13_default>;
1674 #size-cells = <0>;
1680 reg = <0 0x00c8c000 0 0x4000>;
1684 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1688 pinctrl-0 = <&qup_spi13_default>;
1692 #size-cells = <0>;
1698 reg = <0 0x00c90000 0 0x4000>;
1701 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1705 pinctrl-0 = <&qup_i2c14_default>;
1708 #size-cells = <0>;
1714 reg = <0 0x00c90000 0 0x4000>;
1718 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1722 pinctrl-0 = <&qup_spi14_default>;
1726 #size-cells = <0>;
1732 reg = <0 0x00c94000 0 0x4000>;
1735 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1739 pinctrl-0 = <&qup_i2c15_default>;
1742 #size-cells = <0>;
1748 reg = <0 0x00c94000 0 0x4000>;
1752 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1756 pinctrl-0 = <&qup_spi15_default>;
1760 #size-cells = <0>;
1767 reg = <0 0x01500000 0 0x7400>;
1774 reg = <0 0x01620000 0 0x19400>;
1781 reg = <0 0x0163a000 0 0x1000>;
1788 reg = <0 0x016e0000 0 0xd080>;
1795 reg = <0 0x01700000 0 0x20000>;
1802 reg = <0 0x01720000 0 0x7000>;
1809 reg = <0 0x01740000 0 0x1c100>;
1816 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1817 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1818 <0 0x09600000 0 0x50000>;
1826 reg = <0x0 0x010a2000 0x0 0x1000>,
1827 <0x0 0x010ad000 0x0 0x3000>;
1832 reg = <0 0x01c00000 0 0x3000>,
1833 <0 0x60000000 0 0xf1d>,
1834 <0 0x60000f20 0 0xa8>,
1835 <0 0x60001000 0 0x1000>,
1836 <0 0x60100000 0 0x100000>;
1839 linux,pci-domain = <0>;
1840 bus-range = <0x00 0xff>;
1846 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1847 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1868 interrupt-map-mask = <0 0 0 0x7>;
1869 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1870 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1871 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1872 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1887 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1888 <0x100 &apps_smmu 0x1d81 0x1>;
1902 pinctrl-0 = <&pcie0_default_state>;
1906 pcie@0 {
1908 reg = <0x0 0x0 0x0 0x0 0x0>;
1909 bus-range = <0x01 0xff>;
1919 reg = <0 0x01c06000 0 0x1000>;
1932 #clock-cells = <0>;
1934 #phy-cells = <0>;
1947 reg = <0 0x01c08000 0 0x3000>,
1948 <0 0x40000000 0 0xf1d>,
1949 <0 0x40000f20 0 0xa8>,
1950 <0 0x40001000 0 0x1000>,
1951 <0 0x40100000 0 0x100000>;
1955 bus-range = <0x00 0xff>;
1961 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1962 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1983 interrupt-map-mask = <0 0 0 0x7>;
1984 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1985 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1986 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1987 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2005 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2006 <0x100 &apps_smmu 0x1e01 0x1>;
2020 pinctrl-0 = <&pcie1_default_state>;
2024 pcie@0 {
2026 reg = <0x0 0x0 0x0 0x0 0x0>;
2027 bus-range = <0x01 0xff>;
2037 reg = <0 0x01c0e000 0 0x1000>;
2050 #clock-cells = <0>;
2052 #phy-cells = <0>;
2066 reg = <0 0x01d84000 0 0x2500>,
2067 <0 0x01d90000 0 0x8000>;
2077 iommus = <&apps_smmu 0x300 0>;
2101 <0 0>,
2102 <0 0>,
2104 <0 0>,
2105 <0 0>,
2106 <0 0>,
2107 <0 0>,
2108 <0 300000000>;
2115 reg = <0 0x01d87000 0 0x1000>;
2126 resets = <&ufs_mem_hc 0>;
2129 #phy-cells = <0>;
2136 reg = <0 0x01dc4000 0 0x24000>;
2139 qcom,ee = <0>;
2143 iommus = <&apps_smmu 0x502 0x0641>,
2144 <&apps_smmu 0x504 0x0011>,
2145 <&apps_smmu 0x506 0x0011>,
2146 <&apps_smmu 0x508 0x0011>,
2147 <&apps_smmu 0x512 0x0000>;
2152 reg = <0 0x01dfa000 0 0x6000>;
2155 iommus = <&apps_smmu 0x502 0x0641>,
2156 <&apps_smmu 0x504 0x0011>,
2157 <&apps_smmu 0x506 0x0011>,
2158 <&apps_smmu 0x508 0x0011>,
2159 <&apps_smmu 0x512 0x0000>;
2160 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2166 reg = <0x0 0x01f40000 0x0 0x20000>;
2172 reg = <0x0 0x01f60000 0x0 0x20000>;
2177 reg = <0x0 0x02400000 0x0 0x4040>;
2180 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2198 qcom,smem-states = <&slpi_smp2p_out 0>;
2215 #size-cells = <0>;
2220 iommus = <&apps_smmu 0x05a1 0x0>;
2226 iommus = <&apps_smmu 0x05a2 0x0>;
2232 iommus = <&apps_smmu 0x05a3 0x0>;
2241 reg = <0 0x02c00000 0 0x40000>;
2246 iommus = <&adreno_smmu 0 0x401>;
2268 opp-supported-hw = <0x2>;
2274 opp-supported-hw = <0x3>;
2280 opp-supported-hw = <0x3>;
2286 opp-supported-hw = <0x3>;
2292 opp-supported-hw = <0x3>;
2298 opp-supported-hw = <0x3>;
2306 reg = <0 0x02c6a000 0 0x30000>,
2307 <0 0x0b290000 0 0x10000>,
2308 <0 0x0b490000 0 0x10000>;
2326 iommus = <&adreno_smmu 5 0x400>;
2344 reg = <0 0x02c90000 0 0x9000>;
2359 reg = <0 0x02ca0000 0 0x10000>;
2381 reg = <0x0 0x03100000 0x0 0x300000>,
2382 <0x0 0x03500000 0x0 0x300000>,
2383 <0x0 0x03900000 0x0 0x300000>,
2384 <0x0 0x03D00000 0x0 0x300000>;
2387 gpio-ranges = <&tlmm 0 0 176>;
2397 drive-strength = <0x02>;
2730 reg = <0x0 0x04080000 0x0 0x4040>;
2733 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2752 qcom,smem-states = <&modem_smp2p_out 0>;
2767 reg = <0 0x06002000 0 0x1000>,
2768 <0 0x16280000 0 0x180000>;
2785 reg = <0 0x06041000 0 0x1000>;
2800 #size-cells = <0>;
2813 reg = <0 0x06042000 0 0x1000>;
2828 #size-cells = <0>;
2841 reg = <0 0x06043000 0 0x1000>;
2856 #size-cells = <0>;
2869 reg = <0 0x06045000 0 0x1000>;
2884 #size-cells = <0>;
2886 port@0 {
2887 reg = <0>;
2911 reg = <0 0x06046000 0 0x1000>;
2918 #size-cells = <0>;
2920 port@0 {
2921 reg = <0>;
2946 reg = <0 0x06047000 0 0x1000>;
2970 reg = <0 0x06048000 0 0x1000>;
2971 iommus = <&apps_smmu 0x05e0 0x0>;
2988 reg = <0 0x0604a000 0 0x1000>;
2995 #size-cells = <0>;
3017 reg = <0 0x06b08000 0 0x1000>;
3032 #size-cells = <0>;
3045 reg = <0 0x06b09000 0 0x1000>;
3069 reg = <0 0x06b0a000 0 0x1000>;
3094 reg = <0 0x07040000 0 0x1000>;
3114 reg = <0 0x07140000 0 0x1000>;
3134 reg = <0 0x07240000 0 0x1000>;
3154 reg = <0 0x07340000 0 0x1000>;
3174 reg = <0 0x07440000 0 0x1000>;
3194 reg = <0 0x07540000 0 0x1000>;
3214 reg = <0 0x07640000 0 0x1000>;
3234 reg = <0 0x07740000 0 0x1000>;
3254 reg = <0 0x07800000 0 0x1000>;
3269 #size-cells = <0>;
3271 port@0 {
3272 reg = <0>;
3331 reg = <0 0x07810000 0 0x1000>;
3355 reg = <0x0 0x08300000 0x0 0x4040>;
3358 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3374 qcom,smem-states = <&cdsp_smp2p_out 0>;
3391 #size-cells = <0>;
3396 iommus = <&apps_smmu 0x1001 0x0460>;
3402 iommus = <&apps_smmu 0x1002 0x0460>;
3408 iommus = <&apps_smmu 0x1003 0x0460>;
3414 iommus = <&apps_smmu 0x1004 0x0460>;
3420 iommus = <&apps_smmu 0x1005 0x0460>;
3426 iommus = <&apps_smmu 0x1006 0x0460>;
3432 iommus = <&apps_smmu 0x1007 0x0460>;
3438 iommus = <&apps_smmu 0x1008 0x0460>;
3449 reg = <0 0x088e2000 0 0x400>;
3451 #phy-cells = <0>;
3462 reg = <0 0x088e3000 0 0x400>;
3464 #phy-cells = <0>;
3474 reg = <0 0x088e8000 0 0x3000>;
3496 #size-cells = <0>;
3498 port@0 {
3499 reg = <0>;
3525 reg = <0 0x088eb000 0 0x1000>;
3536 #clock-cells = <0>;
3537 #phy-cells = <0>;
3549 reg = <0 0x08804000 0 0x1000>;
3559 iommus = <&apps_smmu 0x6a0 0x0>;
3560 qcom,dll-config = <0x0007642c>;
3561 qcom,ddr-config = <0x80040868>;
3562 power-domains = <&rpmhpd 0>;
3594 reg = <0 0x09160000 0 0x3200>;
3601 reg = <0 0x09680000 0 0x3e200>;
3608 reg = <0 0x0a6f8800 0 0x400>;
3647 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3648 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3653 reg = <0 0x0a600000 0 0xcd00>;
3655 iommus = <&apps_smmu 0x140 0>;
3666 #size-cells = <0>;
3668 port@0 {
3669 reg = <0>;
3688 reg = <0 0x0a8f8800 0 0x400>;
3727 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3733 reg = <0 0x0a800000 0 0xcd00>;
3735 iommus = <&apps_smmu 0x160 0>;
3748 reg = <0 0x0ab00000 0 0x10000>;
3761 reg = <0 0x0ac00000 0 0x1000>;
3768 reg = <0 0x0ad00000 0 0x10000>;
3780 reg = <0 0x0ae00000 0 0x1000>;
3783 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3784 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3799 iommus = <&apps_smmu 0x800 0x420>;
3809 reg = <0 0x0ae01000 0 0x8f000>,
3810 <0 0x0aeb0000 0 0x3000>;
3826 interrupts = <0>;
3830 #size-cells = <0>;
3832 port@0 {
3833 reg = <0>;
3881 reg = <0 0xae90000 0 0x200>,
3882 <0 0xae90200 0 0x200>,
3883 <0 0xae90400 0 0x600>,
3884 <0 0x0ae90a00 0 0x600>,
3885 <0 0x0ae91000 0 0x600>;
3908 #sound-dai-cells = <0>;
3917 #size-cells = <0>;
3919 port@0 {
3920 reg = <0>;
3962 reg = <0 0x0ae94000 0 0x400>;
3994 #size-cells = <0>;
3998 #size-cells = <0>;
4000 port@0 {
4001 reg = <0>;
4036 reg = <0 0x0ae94400 0 0x200>,
4037 <0 0x0ae94600 0 0x280>,
4038 <0 0x0ae94900 0 0x260>;
4044 #phy-cells = <0>;
4055 reg = <0 0x0ae96000 0 0x400>;
4087 #size-cells = <0>;
4091 #size-cells = <0>;
4093 port@0 {
4094 reg = <0>;
4110 reg = <0 0x0ae96400 0 0x200>,
4111 <0 0x0ae96600 0 0x280>,
4112 <0 0x0ae96900 0 0x260>;
4118 #phy-cells = <0>;
4130 reg = <0 0x0af00000 0 0x10000>;
4154 reg = <0 0x0b220000 0 0x30000>;
4155 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4164 reg = <0x0 0x0c300000 0x0 0x400>;
4166 mboxes = <&apss_shared 0>;
4168 #clock-cells = <0>;
4173 reg = <0 0x0c3f0000 0 0x400>;
4178 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4179 <0 0x0c222000 0 0x1ff>; /* SROT */
4189 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4190 <0 0x0c223000 0 0x1ff>; /* SROT */
4200 reg = <0x0 0x0c440000 0x0 0x0001100>,
4201 <0x0 0x0c600000 0x0 0x2000000>,
4202 <0x0 0x0e600000 0x0 0x0100000>,
4203 <0x0 0x0e700000 0x0 0x00a0000>,
4204 <0x0 0x0c40a000 0x0 0x0026000>;
4208 qcom,ee = <0>;
4209 qcom,channel = <0>;
4211 #size-cells = <0>;
4218 reg = <0 0x15000000 0 0x100000>;
4307 reg = <0x0 0x17300000 0x0 0x4040>;
4310 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4326 qcom,smem-states = <&adsp_smp2p_out 0>;
4343 #size-cells = <0>;
4348 iommus = <&apps_smmu 0x1b23 0x0>;
4354 iommus = <&apps_smmu 0x1b24 0x0>;
4360 iommus = <&apps_smmu 0x1b25 0x0>;
4370 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4371 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4378 reg = <0x0 0x17c00000 0x0 0x1000>;
4384 reg = <0 0x17c10000 0 0x1000>;
4386 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4392 ranges = <0 0 0 0x20000000>;
4394 reg = <0x0 0x17c20000 0x0 0x1000>;
4398 frame-number = <0>;
4401 reg = <0x17c21000 0x1000>,
4402 <0x17c22000 0x1000>;
4408 reg = <0x17c23000 0x1000>;
4415 reg = <0x17c25000 0x1000>;
4422 reg = <0x17c26000 0x1000>;
4429 reg = <0x17c29000 0x1000>;
4436 reg = <0x17c2b000 0x1000>;
4443 reg = <0x17c2d000 0x1000>;
4451 reg = <0x0 0x18200000 0x0 0x10000>,
4452 <0x0 0x18210000 0x0 0x10000>,
4453 <0x0 0x18220000 0x0 0x10000>;
4454 reg-names = "drv-0", "drv-1", "drv-2";
4458 qcom,tcs-offset = <0xd00>;
4534 reg = <0 0x18321000 0 0x1400>;
4544 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4545 <0 0x18327800 0 0x1400>;
4558 reg = <0 0x18350800 0 0x400>;
4570 reg = <0 0x18358800 0 0x400>;
4582 reg = <0 0x18800000 0 0x800000>;
4599 iommus = <&apps_smmu 0x0640 0x1>;
4609 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5132 thermal-sensors = <&tsens0 0>;
5217 thermal-sensors = <&tsens1 0>;