Lines Matching +full:0 +full:xae90200
35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x200>;
110 clocks = <&cpufreq_hw 0>;
115 qcom,freq-domain = <&cpufreq_hw 0>;
134 reg = <0x0 0x300>;
135 clocks = <&cpufreq_hw 0>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
159 reg = <0x0 0x400>;
160 clocks = <&cpufreq_hw 0>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
184 reg = <0x0 0x500>;
185 clocks = <&cpufreq_hw 0>;
190 qcom,freq-domain = <&cpufreq_hw 0>;
209 reg = <0x0 0x600>;
234 reg = <0x0 0x700>;
293 cluster_sleep_pc: cluster-sleep-0 {
295 arm,psci-suspend-param = <0x41000044>;
303 arm,psci-suspend-param = <0x41001244>;
311 arm,psci-suspend-param = <0x4100b244>;
321 little_cpu_sleep_0: cpu-sleep-0-0 {
324 arm,psci-suspend-param = <0x40000003>;
331 little_cpu_sleep_1: cpu-sleep-0-1 {
334 arm,psci-suspend-param = <0x40000004>;
341 big_cpu_sleep_0: cpu-sleep-1-0 {
344 arm,psci-suspend-param = <0x40000003>;
354 arm,psci-suspend-param = <0x40000004>;
373 reg = <0x0 0x80000000 0x0 0x0>;
511 #power-domain-cells = <0>;
517 #power-domain-cells = <0>;
523 #power-domain-cells = <0>;
529 #power-domain-cells = <0>;
535 #power-domain-cells = <0>;
541 #power-domain-cells = <0>;
547 #power-domain-cells = <0>;
553 #power-domain-cells = <0>;
559 #power-domain-cells = <0>;
572 reg = <0x0 0x80000000 0x0 0x600000>;
577 reg = <0x0 0x80700000 0x0 0x160000>;
583 reg = <0x0 0x80860000 0x0 0x20000>;
588 reg = <0x0 0x808ff000 0x0 0x1000>;
593 reg = <0x0 0x80900000 0x0 0x200000>;
598 reg = <0x0 0x80b00000 0x0 0x1e00000>;
603 reg = <0x0 0x86000000 0x0 0x500000>;
608 reg = <0x0 0x86500000 0x0 0x500000>;
613 reg = <0x0 0x86a00000 0x0 0x500000>;
618 reg = <0x0 0x86f00000 0x0 0x1e00000>;
623 reg = <0x0 0x88d00000 0x0 0x2800000>;
628 reg = <0x0 0x8b500000 0x0 0x200000>;
633 reg = <0x0 0x8b700000 0x0 0x10000>;
638 reg = <0x0 0x8b710000 0x0 0x5400>;
643 reg = <0x0 0x8b800000 0x0 0xf800000>;
648 reg = <0x0 0xa0000000 0x0 0x2300000>;
653 reg = <0x0 0xa2300000 0x0 0x100000>;
658 reg = <0x0 0xc0000000 0x0 0x3900000>;
663 reg = <0x0 0xf0d00000 0x0 0x1000>;
668 reg = <0x0 0xffb00000 0x0 0xc0000>;
673 reg = <0x0 0xffbc0000 0x0 0x40000>;
679 reg = <0x0 0xffc00000 0x0 0x100000>;
680 record-size = <0x1000>;
681 console-size = <0x40000>;
682 pmsg-size = <0x20000>;
688 reg = <0x0 0xffd00000 0x0 0x1000>;
708 qcom,local-pid = <0>;
732 qcom,local-pid = <0>;
757 qcom,local-pid = <0>;
783 soc: soc@0 {
786 ranges = <0 0 0 0 0x10 0>;
787 dma-ranges = <0 0 0 0 0x10 0>;
792 reg = <0x0 0x00100000 0x0 0x1f0000>;
806 reg = <0x0 0x00408000 0x0 0x1000>;
815 reg = <0x0 0x00784000 0x0 0x3000>;
820 reg = <0x2015 0x1>;
821 bits = <0 8>;
827 reg = <0x0 0x00793000 0x0 0x1000>;
834 reg = <0x0 0x007c4000 0x0 0x1000>,
835 <0x0 0x007c5000 0x0 0x1000>,
836 <0x0 0x007c8000 0x0 0x8000>;
842 iommus = <&apps_smmu 0x60 0x0>;
849 qcom,dll-config = <0x000f642c>;
850 qcom,ddr-config = <0x80040868>;
881 reg = <0x0 0x00800000 0x0 0x60000>;
893 dma-channel-mask = <0x1f>;
894 iommus = <&apps_smmu 0x56 0x0>;
901 reg = <0x0 0x008c0000 0x0 0x2000>;
907 iommus = <&apps_smmu 0x43 0x0>;
913 reg = <0x0 0x00880000 0x0 0x4000>;
917 pinctrl-0 = <&qup_i2c0_default>;
919 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
920 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
923 #size-cells = <0>;
924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
926 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
933 reg = <0x0 0x00884000 0x0 0x4000>;
937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
949 reg = <0x0 0x00888000 0x0 0x4000>;
953 pinctrl-0 = <&qup_i2c2_default>;
955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
959 #size-cells = <0>;
960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
961 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
962 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
970 reg = <0x0 0x00900000 0x0 0x60000>;
982 dma-channel-mask = <0x3f>;
983 iommus = <&apps_smmu 0x4d6 0x0>;
990 reg = <0x0 0x009c0000 0x0 0x2000>;
996 iommus = <&apps_smmu 0x4c3 0x0>;
1002 reg = <0x0 0x00980000 0x0 0x4000>;
1006 pinctrl-0 = <&qup_i2c6_default>;
1008 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1009 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1012 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1014 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1015 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1022 reg = <0x0 0x00984000 0x0 0x4000>;
1026 pinctrl-0 = <&qup_i2c7_default>;
1028 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1032 #size-cells = <0>;
1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1035 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1042 reg = <0x0 0x00988000 0x0 0x4000>;
1046 pinctrl-0 = <&qup_i2c8_default>;
1048 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1052 #size-cells = <0>;
1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1055 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1062 reg = <0x0 0x0098c000 0x0 0x4000>;
1066 pinctrl-0 = <&qup_uart9_default>;
1068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1069 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1076 reg = <0x0 0x00990000 0x0 0x4000>;
1080 pinctrl-0 = <&qup_i2c10_default>;
1082 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1086 #size-cells = <0>;
1087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1088 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1089 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
1097 reg = <0x0 0x01500000 0x0 0x28000>;
1104 reg = <0x0 0x01620000 0x0 0x17080>;
1117 reg = <0x0 0x016e0000 0x0 0x15080>;
1124 reg = <0x0 0x01700000 0x0 0x1f880>;
1137 reg = <0x0 0x01740000 0x0 0x1c100>;
1145 reg = <0x0 0x01d84000 0x0 0x3000>,
1146 <0x0 0x01d90000 0x0 0x8000>;
1158 iommus = <&apps_smmu 0x80 0x0>;
1180 <0 0>,
1181 <0 0>,
1184 <0 0>,
1185 <0 0>,
1186 <0 0>,
1187 <0 0>;
1194 reg = <0x0 0x01d87000 0x0 0x1000>;
1205 resets = <&ufs_mem_hc 0>;
1208 #phy-cells = <0>;
1215 reg = <0x0 0x01dc4000 0x0 0x24000>;
1218 qcom,ee = <0>;
1222 iommus = <&apps_smmu 0x426 0x11>,
1223 <&apps_smmu 0x432 0x0>,
1224 <&apps_smmu 0x436 0x11>,
1225 <&apps_smmu 0x438 0x1>,
1226 <&apps_smmu 0x43f 0x0>;
1231 reg = <0x0 0x01dfa000 0x0 0x6000>;
1234 iommus = <&apps_smmu 0x426 0x11>,
1235 <&apps_smmu 0x432 0x0>,
1236 <&apps_smmu 0x436 0x11>,
1237 <&apps_smmu 0x438 0x1>,
1238 <&apps_smmu 0x43f 0x0>;
1247 iommus = <&apps_smmu 0x440 0x0>,
1248 <&apps_smmu 0x442 0x0>;
1249 reg = <0x0 0x01e40000 0x0 0x8000>,
1250 <0x0 0x01e50000 0x0 0x3000>,
1251 <0x0 0x01e04000 0x0 0x23000>;
1258 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1268 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
1269 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
1273 qcom,smem-states = <&ipa_smp2p_out 0>,
1283 reg = <0x0 0x01f40000 0x0 0x40000>;
1289 reg = <0x0 0x03000000 0x0 0x10000>;
1292 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1310 qcom,smem-states = <&smp2p_adsp_out 0>;
1330 #size-cells = <0>;
1346 #size-cells = <0>;
1364 #size-cells = <0>;
1366 iommus = <&apps_smmu 0x1001 0x0>;
1377 #sound-dai-cells = <0>;
1388 #size-cells = <0>;
1393 iommus = <&apps_smmu 0x1003 0x0>;
1399 iommus = <&apps_smmu 0x1004 0x0>;
1405 iommus = <&apps_smmu 0x1005 0x0>;
1414 reg = <0x0 0x03d00000 0x0 0x40000>,
1415 <0x0 0x03d9e000 0x0 0x1000>;
1420 iommus = <&adreno_smmu 0>;
1439 opp-supported-hw = <0x03>;
1445 opp-supported-hw = <0x07>;
1451 opp-supported-hw = <0x0f>;
1457 opp-supported-hw = <0x1f>;
1463 opp-supported-hw = <0x1f>;
1469 opp-supported-hw = <0x1f>;
1475 opp-supported-hw = <0x1f>;
1482 reg = <0x0 0x03d40000 0x0 0x10000>;
1508 reg = <0x0 0x03d6a000 0x0 0x31000>,
1509 <0x0 0x0b290000 0x0 0x10000>,
1510 <0x0 0x0b490000 0x0 0x10000>;
1552 reg = <0x0 0x03d90000 0x0 0x9000>;
1566 reg = <0x0 0x04080000 0x0 0x10000>;
1569 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1588 qcom,smem-states = <&modem_smp2p_out 0>;
1606 reg = <0x0 0x08300000 0x0 0x10000>;
1609 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1627 qcom,smem-states = <&smp2p_cdsp_out 0>;
1648 #size-cells = <0>;
1653 iommus = <&apps_smmu 0x1401 0x20>;
1659 iommus = <&apps_smmu 0x1402 0x20>;
1665 iommus = <&apps_smmu 0x1403 0x20>;
1671 iommus = <&apps_smmu 0x1404 0x20>;
1677 iommus = <&apps_smmu 0x1405 0x20>;
1683 iommus = <&apps_smmu 0x1406 0x20>;
1689 iommus = <&apps_smmu 0x1407 0x20>;
1695 iommus = <&apps_smmu 0x1408 0x20>;
1705 reg = <0x0 0x08804000 0x0 0x1000>;
1710 iommus = <&apps_smmu 0x560 0x0>;
1717 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
1718 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
1721 pinctrl-0 = <&sdc2_on_state>;
1725 qcom,dll-config = <0x0007642c>;
1726 qcom,ddr-config = <0x80040868>;
1754 reg = <0x0 0x088e3000 0x0 0x400>;
1756 #phy-cells = <0>;
1766 reg = <0x0 0x088e8000 0x0 0x3000>;
1789 #size-cells = <0>;
1791 port@0 {
1792 reg = <0>;
1817 reg = <0x0 0x09160000 0x0 0x3200>;
1824 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>;
1830 reg = <0x0 0x09680000 0x0 0x3e200>;
1837 reg = <0x0 0x09990000 0x0 0x1600>;
1844 reg = <0x0 0x090b6300 0x0 0x600>;
1854 opp-0 {
1883 reg = <0x0 0x090cd000 0x0 0x1000>;
1893 opp-0 {
1941 reg = <0x0 0x0a6f8800 0x0 0x400>;
1973 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
1974 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1979 reg = <0x0 0x0a600000 0x0 0xcd00>;
1981 iommus = <&apps_smmu 0x540 0x0>;
1985 snps,hird-threshold = /bits/ 8 <0x10>;
1995 #size-cells = <0>;
1997 port@0 {
1998 reg = <0>;
2017 reg = <0x0 0x0aaf0000 0x0 0x10000>;
2031 reg = <0x0 0x0ac4a000 0x0 0x1000>;
2052 pinctrl-0 = <&cci0_default &cci1_default>;
2057 #size-cells = <0>;
2061 cci0_i2c0: i2c-bus@0 {
2062 reg = <0>;
2065 #size-cells = <0>;
2072 #size-cells = <0>;
2078 reg = <0x0 0x0ac4b000 0x0 0x1000>;
2099 pinctrl-0 = <&cci2_default>;
2104 #size-cells = <0>;
2108 cci1_i2c0: i2c-bus@0 {
2109 reg = <0>;
2112 #size-cells = <0>;
2120 reg = <0x0 0x0ad00000 0x0 0x16000>;
2129 reg = <0x0 0x0ae00000 0x0 0x1000>;
2151 iommus = <&apps_smmu 0x800 0x2>;
2161 reg = <0x0 0x0ae01000 0x0 0x8f000>,
2162 <0x0 0x0aeb0000 0x0 0x2008>;
2166 interrupts = <0>;
2189 #size-cells = <0>;
2191 port@0 {
2192 reg = <0>;
2245 reg = <0x0 0xae90000 0x0 0x200>,
2246 <0x0 0xae90200 0x0 0x200>,
2247 <0x0 0xae90400 0x0 0x600>,
2248 <0x0 0xae91000 0x0 0x400>,
2249 <0x0 0xae91400 0x0 0x400>;
2271 #sound-dai-cells = <0>;
2280 #size-cells = <0>;
2282 port@0 {
2283 reg = <0>;
2325 reg = <0x0 0x0ae94000 0x0 0x400>;
2356 #size-cells = <0>;
2362 #size-cells = <0>;
2364 port@0 {
2365 reg = <0>;
2402 reg = <0x0 0x0ae94400 0x0 0x200>,
2403 <0x0 0x0ae94600 0x0 0x280>,
2404 <0x0 0x0ae94a00 0x0 0x1e0>;
2410 #phy-cells = <0>;
2422 reg = <0x0 0x0af00000 0x0 0x20000>;
2442 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>;
2443 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2452 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */
2453 <0x0 0x0c222000 0x0 0x8>; /* SROT */
2463 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */
2464 <0x0 0x0c223000 0x0 0x8>; /* SROT */
2474 reg = <0x0 0x0c300000 0x0 0x1000>;
2479 #clock-cells = <0>;
2484 reg = <0x0 0x0c440000 0x0 0x1100>,
2485 <0x0 0x0c600000 0x0 0x2000000>,
2486 <0x0 0x0e600000 0x0 0x100000>,
2487 <0x0 0x0e700000 0x0 0xa0000>,
2488 <0x0 0x0c40a000 0x0 0x26000>;
2492 qcom,ee = <0>;
2493 qcom,channel = <0>;
2495 #size-cells = <0>;
2502 reg = <0x0 0x0f100000 0x0 0x300000>;
2516 gpio-ranges = <&tlmm 0 0 157>;
2681 reg = <0x0 0x15000000 0x0 0x100000>;
2772 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2773 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2779 reg = <0x0 0x17c10000 0x0 0x1000>;
2781 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
2786 reg = <0x0 0x17c20000 0x0 0x1000>;
2790 ranges = <0 0 0 0x20000000>;
2793 frame-number = <0>;
2796 reg = <0x17c21000 0x1000>,
2797 <0x17c22000 0x1000>;
2803 reg = <0x17c23000 0x1000>;
2810 reg = <0x17c25000 0x1000>;
2817 reg = <0x17c27000 0x1000>;
2824 reg = <0x17c29000 0x1000>;
2831 reg = <0x17c2b000 0x1000>;
2838 reg = <0x17c2d000 0x1000>;
2846 reg = <0x0 0x18200000 0x0 0x10000>,
2847 <0x0 0x18210000 0x0 0x10000>,
2848 <0x0 0x18220000 0x0 0x10000>;
2849 reg-names = "drv-0", "drv-1", "drv-2";
2853 qcom,tcs-offset = <0xd00>;
2923 reg = <0x0 0x18321000 0x0 0x1000>;
2933 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>;
2944 reg = <0x0 0x18800000 0x0 0x800000>;
2959 iommus = <&apps_smmu 0x20 0x1>;
2967 thermal-sensors = <&tsens0 0>;
2972 hysteresis = <0>;
2979 thermal-sensors = <&tsens1 0>;
2984 hysteresis = <0>;
2996 hysteresis = <0>;
3008 hysteresis = <0>;
3026 hysteresis = <0>;
3051 hysteresis = <0>;
3076 hysteresis = <0>;
3101 hysteresis = <0>;
3126 hysteresis = <0>;
3151 hysteresis = <0>;
3176 hysteresis = <0>;
3201 hysteresis = <0>;
3226 hysteresis = <0>;
3251 hysteresis = <0>;
3270 hysteresis = <0>;
3282 hysteresis = <0>;
3294 hysteresis = <0>;
3306 hysteresis = <0>;
3372 hysteresis = <0>;
3384 hysteresis = <0>;
3396 hysteresis = <0>;
3408 hysteresis = <0>;
3420 hysteresis = <0>;
3432 hysteresis = <0>;
3444 hysteresis = <0>;
3457 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;