Lines Matching +full:0 +full:x008c0000
79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
151 reg = <0x0 0x200>;
152 clocks = <&cpufreq_hw 0>;
156 qcom,freq-domain = <&cpufreq_hw 0>;
175 reg = <0x0 0x300>;
176 clocks = <&cpufreq_hw 0>;
180 qcom,freq-domain = <&cpufreq_hw 0>;
199 reg = <0x0 0x400>;
223 reg = <0x0 0x500>;
247 reg = <0x0 0x600>;
271 reg = <0x0 0x700>;
331 little_cpu_sleep_0: cpu-sleep-0-0 {
334 arm,psci-suspend-param = <0x40000004>;
341 big_cpu_sleep_0: cpu-sleep-1-0 {
344 arm,psci-suspend-param = <0x40000004>;
353 cluster_sleep_0: cluster-sleep-0 {
355 arm,psci-suspend-param = <0x4100c244>;
372 reg = <0 0x80000000 0 0>;
722 #power-domain-cells = <0>;
728 #power-domain-cells = <0>;
734 #power-domain-cells = <0>;
740 #power-domain-cells = <0>;
746 #power-domain-cells = <0>;
752 #power-domain-cells = <0>;
758 #power-domain-cells = <0>;
764 #power-domain-cells = <0>;
770 #power-domain-cells = <0>;
781 reg = <0 0x85700000 0 0x600000>;
786 reg = <0 0x85e00000 0 0x100000>;
791 reg = <0 0x85fc0000 0 0x20000>;
797 reg = <0x0 0x85fe0000 0 0x20000>;
803 reg = <0x0 0x86000000 0 0x200000>;
809 reg = <0 0x86200000 0 0x2d00000>;
815 reg = <0 0x88f00000 0 0x200000>;
823 reg = <0 0x8ab00000 0 0x1400000>;
828 reg = <0 0x8bf00000 0 0x500000>;
833 reg = <0 0x8c400000 0 0x10000>;
838 reg = <0 0x8c410000 0 0x5000>;
843 reg = <0 0x8c415000 0 0x2000>;
848 reg = <0 0x8c500000 0 0x1a00000>;
853 reg = <0 0x8df00000 0 0x100000>;
858 reg = <0 0x8e000000 0 0x7800000>;
863 reg = <0 0x95800000 0 0x500000>;
868 reg = <0 0x95d00000 0 0x800000>;
873 reg = <0 0x96500000 0 0x200000>;
878 reg = <0 0x96700000 0 0x1400000>;
883 reg = <0 0x97b00000 0 0x100000>;
888 alloc-ranges = <0 0xa0000000 0 0x20000000>;
889 size = <0 0x4000>;
895 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
896 alignment = <0x0 0x400000>;
897 size = <0x0 0x1000000>;
906 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
920 qcom,smem-states = <&adsp_smp2p_out 0>;
936 #size-cells = <0>;
952 #size-cells = <0>;
964 #size-cells = <0>;
966 iommus = <&apps_smmu 0x1821 0x0>;
976 #sound-dai-cells = <0>;
987 #size-cells = <0>;
992 iommus = <&apps_smmu 0x1823 0x0>;
998 iommus = <&apps_smmu 0x1824 0x0>;
1008 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1022 qcom,smem-states = <&cdsp_smp2p_out 0>;
1038 #size-cells = <0>;
1043 iommus = <&apps_smmu 0x1401 0x30>;
1049 iommus = <&apps_smmu 0x1402 0x30>;
1055 iommus = <&apps_smmu 0x1403 0x30>;
1061 iommus = <&apps_smmu 0x1404 0x30>;
1067 iommus = <&apps_smmu 0x1405 0x30>;
1073 iommus = <&apps_smmu 0x1406 0x30>;
1079 iommus = <&apps_smmu 0x1407 0x30>;
1085 iommus = <&apps_smmu 0x1408 0x30>;
1099 qcom,local-pid = <0>;
1123 qcom,local-pid = <0>;
1144 qcom,local-pid = <0>;
1175 qcom,local-pid = <0>;
1190 soc: soc@0 {
1193 ranges = <0 0 0 0 0x10 0>;
1194 dma-ranges = <0 0 0 0 0x10 0>;
1199 reg = <0 0x00100000 0 0x1f0000>;
1218 reg = <0 0x00784000 0 0x8ff>;
1223 reg = <0x1eb 0x1>;
1228 reg = <0x1eb 0x2>;
1235 reg = <0 0x00793000 0 0x1000>;
1243 reg = <0 0x00800000 0 0x60000>;
1258 dma-channel-mask = <0xfa>;
1259 iommus = <&apps_smmu 0x0016 0x0>;
1265 reg = <0 0x008c0000 0 0x6000>;
1269 iommus = <&apps_smmu 0x3 0x0>;
1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1279 reg = <0 0x00880000 0 0x4000>;
1283 pinctrl-0 = <&qup_i2c0_default>;
1286 #size-cells = <0>;
1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1291 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1293 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1294 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1301 reg = <0 0x00880000 0 0x4000>;
1305 pinctrl-0 = <&qup_spi0_default>;
1308 #size-cells = <0>;
1309 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1310 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1312 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1313 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1320 reg = <0 0x00880000 0 0x4000>;
1324 pinctrl-0 = <&qup_uart0_default>;
1328 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1329 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1336 reg = <0 0x00884000 0 0x4000>;
1340 pinctrl-0 = <&qup_i2c1_default>;
1343 #size-cells = <0>;
1346 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1347 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1348 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1350 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1358 reg = <0 0x00884000 0 0x4000>;
1362 pinctrl-0 = <&qup_spi1_default>;
1365 #size-cells = <0>;
1366 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1367 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1369 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1377 reg = <0 0x00884000 0 0x4000>;
1381 pinctrl-0 = <&qup_uart1_default>;
1385 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1386 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1393 reg = <0 0x00888000 0 0x4000>;
1397 pinctrl-0 = <&qup_i2c2_default>;
1400 #size-cells = <0>;
1403 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1404 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1405 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1415 reg = <0 0x00888000 0 0x4000>;
1419 pinctrl-0 = <&qup_spi2_default>;
1422 #size-cells = <0>;
1423 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1424 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1426 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1434 reg = <0 0x00888000 0 0x4000>;
1438 pinctrl-0 = <&qup_uart2_default>;
1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1450 reg = <0 0x0088c000 0 0x4000>;
1454 pinctrl-0 = <&qup_i2c3_default>;
1457 #size-cells = <0>;
1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1464 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1472 reg = <0 0x0088c000 0 0x4000>;
1476 pinctrl-0 = <&qup_spi3_default>;
1479 #size-cells = <0>;
1480 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1481 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1483 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1491 reg = <0 0x0088c000 0 0x4000>;
1495 pinctrl-0 = <&qup_uart3_default>;
1499 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1500 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1507 reg = <0 0x00890000 0 0x4000>;
1511 pinctrl-0 = <&qup_i2c4_default>;
1514 #size-cells = <0>;
1517 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1518 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1519 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1529 reg = <0 0x00890000 0 0x4000>;
1533 pinctrl-0 = <&qup_spi4_default>;
1536 #size-cells = <0>;
1537 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1538 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1540 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1548 reg = <0 0x00890000 0 0x4000>;
1552 pinctrl-0 = <&qup_uart4_default>;
1556 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1557 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1564 reg = <0 0x00894000 0 0x4000>;
1568 pinctrl-0 = <&qup_i2c5_default>;
1571 #size-cells = <0>;
1574 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1575 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1576 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1586 reg = <0 0x00894000 0 0x4000>;
1590 pinctrl-0 = <&qup_spi5_default>;
1593 #size-cells = <0>;
1594 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1595 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1597 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1605 reg = <0 0x00894000 0 0x4000>;
1609 pinctrl-0 = <&qup_uart5_default>;
1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1621 reg = <0 0x00898000 0 0x4000>;
1625 pinctrl-0 = <&qup_i2c6_default>;
1628 #size-cells = <0>;
1631 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1632 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1633 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1635 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1643 reg = <0 0x00898000 0 0x4000>;
1647 pinctrl-0 = <&qup_spi6_default>;
1650 #size-cells = <0>;
1651 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1652 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1654 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1662 reg = <0 0x00898000 0 0x4000>;
1666 pinctrl-0 = <&qup_uart6_default>;
1670 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1671 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1678 reg = <0 0x0089c000 0 0x4000>;
1682 pinctrl-0 = <&qup_i2c7_default>;
1685 #size-cells = <0>;
1693 reg = <0 0x0089c000 0 0x4000>;
1697 pinctrl-0 = <&qup_spi7_default>;
1700 #size-cells = <0>;
1701 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1704 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1712 reg = <0 0x0089c000 0 0x4000>;
1716 pinctrl-0 = <&qup_uart7_default>;
1720 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1721 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1730 reg = <0 0x00a00000 0 0x60000>;
1745 dma-channel-mask = <0xfa>;
1746 iommus = <&apps_smmu 0x06d6 0x0>;
1752 reg = <0 0x00ac0000 0 0x6000>;
1756 iommus = <&apps_smmu 0x6c3 0x0>;
1760 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1766 reg = <0 0x00a80000 0 0x4000>;
1770 pinctrl-0 = <&qup_i2c8_default>;
1773 #size-cells = <0>;
1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1780 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1781 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1788 reg = <0 0x00a80000 0 0x4000>;
1792 pinctrl-0 = <&qup_spi8_default>;
1795 #size-cells = <0>;
1796 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1797 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1799 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1800 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1807 reg = <0 0x00a80000 0 0x4000>;
1811 pinctrl-0 = <&qup_uart8_default>;
1815 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1816 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1823 reg = <0 0x00a84000 0 0x4000>;
1827 pinctrl-0 = <&qup_i2c9_default>;
1830 #size-cells = <0>;
1833 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1834 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1835 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1837 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1845 reg = <0 0x00a84000 0 0x4000>;
1849 pinctrl-0 = <&qup_spi9_default>;
1852 #size-cells = <0>;
1853 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1854 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1856 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1864 reg = <0 0x00a84000 0 0x4000>;
1868 pinctrl-0 = <&qup_uart9_default>;
1872 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1873 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1880 reg = <0 0x00a88000 0 0x4000>;
1884 pinctrl-0 = <&qup_i2c10_default>;
1887 #size-cells = <0>;
1890 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1891 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1892 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1894 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1902 reg = <0 0x00a88000 0 0x4000>;
1906 pinctrl-0 = <&qup_spi10_default>;
1909 #size-cells = <0>;
1910 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1911 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1921 reg = <0 0x00a88000 0 0x4000>;
1925 pinctrl-0 = <&qup_uart10_default>;
1929 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1930 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1937 reg = <0 0x00a8c000 0 0x4000>;
1941 pinctrl-0 = <&qup_i2c11_default>;
1944 #size-cells = <0>;
1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1949 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1951 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1959 reg = <0 0x00a8c000 0 0x4000>;
1963 pinctrl-0 = <&qup_spi11_default>;
1966 #size-cells = <0>;
1967 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1968 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1970 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1978 reg = <0 0x00a8c000 0 0x4000>;
1982 pinctrl-0 = <&qup_uart11_default>;
1986 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1987 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1994 reg = <0 0x00a90000 0 0x4000>;
1998 pinctrl-0 = <&qup_i2c12_default>;
2001 #size-cells = <0>;
2004 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2005 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2006 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2008 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2016 reg = <0 0x00a90000 0 0x4000>;
2020 pinctrl-0 = <&qup_spi12_default>;
2023 #size-cells = <0>;
2024 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2027 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2035 reg = <0 0x00a90000 0 0x4000>;
2039 pinctrl-0 = <&qup_uart12_default>;
2043 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2044 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2051 reg = <0 0x00a94000 0 0x4000>;
2055 pinctrl-0 = <&qup_i2c13_default>;
2058 #size-cells = <0>;
2061 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2062 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2063 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2073 reg = <0 0x00a94000 0 0x4000>;
2077 pinctrl-0 = <&qup_spi13_default>;
2080 #size-cells = <0>;
2081 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2082 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2084 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2092 reg = <0 0x00a94000 0 0x4000>;
2096 pinctrl-0 = <&qup_uart13_default>;
2100 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2101 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2108 reg = <0 0x00a98000 0 0x4000>;
2112 pinctrl-0 = <&qup_i2c14_default>;
2115 #size-cells = <0>;
2118 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2120 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2122 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2130 reg = <0 0x00a98000 0 0x4000>;
2134 pinctrl-0 = <&qup_spi14_default>;
2137 #size-cells = <0>;
2138 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2139 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2141 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2149 reg = <0 0x00a98000 0 0x4000>;
2153 pinctrl-0 = <&qup_uart14_default>;
2157 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2165 reg = <0 0x00a9c000 0 0x4000>;
2169 pinctrl-0 = <&qup_i2c15_default>;
2172 #size-cells = <0>;
2176 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2178 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2180 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2187 reg = <0 0x00a9c000 0 0x4000>;
2191 pinctrl-0 = <&qup_spi15_default>;
2194 #size-cells = <0>;
2195 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2196 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2198 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2206 reg = <0 0x00a9c000 0 0x4000>;
2210 pinctrl-0 = <&qup_uart15_default>;
2214 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2215 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2223 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2224 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2225 <0 0x01300000 0 0x50000>;
2233 reg = <0x0 0x010a2000 0x0 0x1000>,
2234 <0x0 0x010ae000 0x0 0x2000>;
2239 reg = <0 0x0114a000 0 0x1000>;
2256 opp-0 {
2276 reg = <0 0x01436400 0 0x600>;
2293 opp-0 {
2313 reg = <0 0x01c00000 0 0x2000>,
2314 <0 0x60000000 0 0xf1d>,
2315 <0 0x60000f20 0 0xa8>,
2316 <0 0x60100000 0 0x100000>,
2317 <0 0x01c07000 0 0x1000>;
2320 linux,pci-domain = <0>;
2321 bus-range = <0x00 0xff>;
2327 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2328 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2349 interrupt-map-mask = <0 0 0 0x7>;
2350 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2351 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2352 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2353 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2370 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2371 <0x100 &apps_smmu 0x1c11 0x1>,
2372 <0x200 &apps_smmu 0x1c12 0x1>,
2373 <0x300 &apps_smmu 0x1c13 0x1>,
2374 <0x400 &apps_smmu 0x1c14 0x1>,
2375 <0x500 &apps_smmu 0x1c15 0x1>,
2376 <0x600 &apps_smmu 0x1c16 0x1>,
2377 <0x700 &apps_smmu 0x1c17 0x1>,
2378 <0x800 &apps_smmu 0x1c18 0x1>,
2379 <0x900 &apps_smmu 0x1c19 0x1>,
2380 <0xa00 &apps_smmu 0x1c1a 0x1>,
2381 <0xb00 &apps_smmu 0x1c1b 0x1>,
2382 <0xc00 &apps_smmu 0x1c1c 0x1>,
2383 <0xd00 &apps_smmu 0x1c1d 0x1>,
2384 <0xe00 &apps_smmu 0x1c1e 0x1>,
2385 <0xf00 &apps_smmu 0x1c1f 0x1>;
2397 pcie@0 {
2399 reg = <0x0 0x0 0x0 0x0 0x0>;
2400 bus-range = <0x01 0xff>;
2410 reg = <0 0x01c06000 0 0x1000>;
2423 #clock-cells = <0>;
2425 #phy-cells = <0>;
2438 reg = <0 0x01c08000 0 0x2000>,
2439 <0 0x40000000 0 0xf1d>,
2440 <0 0x40000f20 0 0xa8>,
2441 <0 0x40100000 0 0x100000>,
2442 <0 0x01c0c000 0 0x1000>;
2446 bus-range = <0x00 0xff>;
2452 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2453 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2474 interrupt-map-mask = <0 0 0 0x7>;
2475 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2476 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2477 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2478 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2500 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2501 <0x100 &apps_smmu 0x1c01 0x1>,
2502 <0x200 &apps_smmu 0x1c02 0x1>,
2503 <0x300 &apps_smmu 0x1c03 0x1>,
2504 <0x400 &apps_smmu 0x1c04 0x1>,
2505 <0x500 &apps_smmu 0x1c05 0x1>,
2506 <0x600 &apps_smmu 0x1c06 0x1>,
2507 <0x700 &apps_smmu 0x1c07 0x1>,
2508 <0x800 &apps_smmu 0x1c08 0x1>,
2509 <0x900 &apps_smmu 0x1c09 0x1>,
2510 <0xa00 &apps_smmu 0x1c0a 0x1>,
2511 <0xb00 &apps_smmu 0x1c0b 0x1>,
2512 <0xc00 &apps_smmu 0x1c0c 0x1>,
2513 <0xd00 &apps_smmu 0x1c0d 0x1>,
2514 <0xe00 &apps_smmu 0x1c0e 0x1>,
2515 <0xf00 &apps_smmu 0x1c0f 0x1>;
2527 pcie@0 {
2529 reg = <0x0 0x0 0x0 0x0 0x0>;
2530 bus-range = <0x01 0xff>;
2540 reg = <0 0x01c0a000 0 0x2000>;
2553 #clock-cells = <0>;
2555 #phy-cells = <0>;
2568 reg = <0 0x01380000 0 0x27200>;
2575 reg = <0 0x014e0000 0 0x400>;
2582 reg = <0 0x01500000 0 0x5080>;
2589 reg = <0 0x01620000 0 0x18080>;
2596 reg = <0 0x016e0000 0 0x15080>;
2603 reg = <0 0x01700000 0 0x1f300>;
2610 reg = <0 0x01740000 0 0x1c100>;
2618 reg = <0 0x01d84000 0 0x2500>,
2619 <0 0x01d90000 0 0x8000>;
2630 iommus = <&apps_smmu 0x100 0xf>;
2655 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2656 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2666 /bits/ 64 <0>,
2667 /bits/ 64 <0>,
2669 /bits/ 64 <0>,
2670 /bits/ 64 <0>,
2671 /bits/ 64 <0>,
2672 /bits/ 64 <0>,
2679 /bits/ 64 <0>,
2680 /bits/ 64 <0>,
2682 /bits/ 64 <0>,
2683 /bits/ 64 <0>,
2684 /bits/ 64 <0>,
2685 /bits/ 64 <0>,
2694 reg = <0 0x01d87000 0 0x1000>;
2705 resets = <&ufs_mem_hc 0>;
2708 #phy-cells = <0>;
2714 reg = <0 0x01dc4000 0 0x24000>;
2719 qcom,ee = <0>;
2721 iommus = <&apps_smmu 0x704 0x1>,
2722 <&apps_smmu 0x706 0x1>,
2723 <&apps_smmu 0x714 0x1>,
2724 <&apps_smmu 0x716 0x1>;
2729 reg = <0 0x01dfa000 0 0x6000>;
2736 iommus = <&apps_smmu 0x704 0x1>,
2737 <&apps_smmu 0x706 0x1>,
2738 <&apps_smmu 0x714 0x1>,
2739 <&apps_smmu 0x716 0x1>;
2745 iommus = <&apps_smmu 0x720 0x0>,
2746 <&apps_smmu 0x722 0x0>;
2747 reg = <0 0x01e40000 0 0x7000>,
2748 <0 0x01e47000 0 0x2000>,
2749 <0 0x01e04000 0 0x2c000>;
2756 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2766 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2767 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2768 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2773 qcom,smem-states = <&ipa_smp2p_out 0>,
2783 reg = <0 0x01f40000 0 0x20000>;
2789 reg = <0 0x01f60000 0 0x20000>;
2794 reg = <0 0x03400000 0 0xc00000>;
2800 gpio-ranges = <&tlmm 0 0 151>;
3333 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3338 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3360 qcom,smem-states = <&modem_smp2p_out 0>;
3367 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3398 reg = <0 0x05090000 0 0x9000>;
3412 reg = <0 0x5c00000 0 0x4000>;
3415 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3433 qcom,smem-states = <&slpi_smp2p_out 0>;
3453 #size-cells = <0>;
3455 compute-cb@0 {
3457 reg = <0>;
3465 reg = <0 0x06002000 0 0x1000>,
3466 <0 0x16280000 0 0x180000>;
3484 reg = <0 0x06041000 0 0x1000>;
3500 #size-cells = <0>;
3513 reg = <0 0x06043000 0 0x1000>;
3529 #size-cells = <0>;
3543 reg = <0 0x06045000 0 0x1000>;
3558 #size-cells = <0>;
3560 port@0 {
3561 reg = <0>;
3580 reg = <0 0x06046000 0 0x1000>;
3604 reg = <0 0x06047000 0 0x1000>;
3631 reg = <0 0x06048000 0 0x1000>;
3649 reg = <0 0x07040000 0 0x1000>;
3669 reg = <0 0x07140000 0 0x1000>;
3689 reg = <0 0x07240000 0 0x1000>;
3709 reg = <0 0x07340000 0 0x1000>;
3729 reg = <0 0x07440000 0 0x1000>;
3749 reg = <0 0x07540000 0 0x1000>;
3769 reg = <0 0x07640000 0 0x1000>;
3789 reg = <0 0x07740000 0 0x1000>;
3809 reg = <0 0x07800000 0 0x1000>;
3825 #size-cells = <0>;
3827 port@0 {
3828 reg = <0>;
3895 reg = <0 0x07810000 0 0x1000>;
3921 reg = <0 0x08804000 0 0x1000>;
3931 iommus = <&apps_smmu 0xa0 0xf>;
3964 reg = <0 0x088df000 0 0x600>;
3965 iommus = <&apps_smmu 0x160 0x0>;
3967 #size-cells = <0>;
3979 reg = <0 0x171c0000 0 0x2c000>;
3985 iommus = <&apps_smmu 0x1806 0x0>;
3987 #size-cells = <0>;
3993 reg = <0 0x17d70800 0 0x400>;
4005 reg = <0 0x17d78800 0 0x400>;
4017 reg = <0 0x088e2000 0 0x400>;
4019 #phy-cells = <0>;
4032 reg = <0 0x088e3000 0 0x400>;
4034 #phy-cells = <0>;
4047 reg = <0 0x088e8000 0 0x3000>;
4071 #size-cells = <0>;
4073 port@0 {
4074 reg = <0>;
4100 reg = <0 0x088eb000 0 0x1000>;
4113 #clock-cells = <0>;
4114 #phy-cells = <0>;
4126 reg = <0 0x0a6f8800 0 0x400>;
4163 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4164 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4169 reg = <0 0x0a600000 0 0xcd00>;
4171 iommus = <&apps_smmu 0x740 0>;
4182 #size-cells = <0>;
4184 port@0 {
4185 reg = <0>;
4204 reg = <0 0x0a8f8800 0 0x400>;
4241 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4242 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4247 reg = <0 0x0a800000 0 0xcd00>;
4249 iommus = <&apps_smmu 0x760 0>;
4262 reg = <0 0x0aa00000 0 0xff000>;
4280 iommus = <&apps_smmu 0x10a0 0x8>,
4281 <&apps_smmu 0x10b0 0x0>;
4283 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4284 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4334 reg = <0 0x0ab00000 0 0x10000>;
4345 reg = <0 0x0acb3000 0 0x1000>,
4346 <0 0x0acba000 0 0x1000>,
4347 <0 0x0acc8000 0 0x1000>,
4348 <0 0x0ac65000 0 0x1000>,
4349 <0 0x0ac66000 0 0x1000>,
4350 <0 0x0ac67000 0 0x1000>,
4351 <0 0x0ac68000 0 0x1000>,
4352 <0 0x0acaf000 0 0x4000>,
4353 <0 0x0acb6000 0 0x4000>,
4354 <0 0x0acc4000 0 0x4000>;
4464 iommus = <&apps_smmu 0x0808 0x0>,
4465 <&apps_smmu 0x0810 0x8>,
4466 <&apps_smmu 0x0c08 0x0>,
4467 <&apps_smmu 0x0c10 0x8>;
4473 #size-cells = <0>;
4475 port@0 {
4476 reg = <0>;
4496 #size-cells = <0>;
4498 reg = <0 0x0ac4a000 0 0x4000>;
4520 pinctrl-0 = <&cci0_default &cci1_default>;
4525 cci_i2c0: i2c-bus@0 {
4526 reg = <0>;
4529 #size-cells = <0>;
4536 #size-cells = <0>;
4542 reg = <0 0x0ad00000 0 0x10000>;
4552 reg = <0 0x0ae00000 0 0x1000>;
4565 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4566 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4569 iommus = <&apps_smmu 0x880 0x8>,
4570 <&apps_smmu 0xc80 0x8>;
4580 reg = <0 0x0ae01000 0 0x8f000>,
4581 <0 0x0aeb0000 0 0x3000>;
4597 interrupts = <0>;
4601 #size-cells = <0>;
4603 port@0 {
4604 reg = <0>;
4654 reg = <0 0x0ae90000 0 0x200>,
4655 <0 0x0ae90200 0 0x200>,
4656 <0 0x0ae90400 0 0x600>,
4657 <0 0x0ae90a00 0 0x600>,
4658 <0 0x0ae91000 0 0x600>;
4682 #size-cells = <0>;
4683 port@0 {
4684 reg = <0>;
4726 reg = <0 0x0ae94000 0 0x400>;
4757 #size-cells = <0>;
4761 #size-cells = <0>;
4763 port@0 {
4764 reg = <0>;
4780 reg = <0 0x0ae94400 0 0x200>,
4781 <0 0x0ae94600 0 0x280>,
4782 <0 0x0ae94a00 0 0x1e0>;
4788 #phy-cells = <0>;
4800 reg = <0 0x0ae96000 0 0x400>;
4831 #size-cells = <0>;
4835 #size-cells = <0>;
4837 port@0 {
4838 reg = <0>;
4854 reg = <0 0x0ae96400 0 0x200>,
4855 <0 0x0ae96600 0 0x280>,
4856 <0 0x0ae96a00 0 0x10e>;
4862 #phy-cells = <0>;
4875 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4885 iommus = <&adreno_smmu 0>;
4892 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4946 reg = <0 0x05040000 0 0x10000>;
4969 reg = <0 0x0506a000 0 0x30000>,
4970 <0 0x0b280000 0 0x10000>,
4971 <0 0x0b480000 0 0x10000>;
5009 reg = <0 0x0af00000 0 0x10000>;
5035 reg = <0 0x0b220000 0 0x30000>;
5036 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
5044 reg = <0 0x0b2e0000 0 0x20000>;
5050 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5051 <0 0x0c222000 0 0x1ff>; /* SROT */
5061 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5062 <0 0x0c223000 0 0x1ff>; /* SROT */
5072 reg = <0 0x0c2a0000 0 0x31000>;
5078 reg = <0 0x0c300000 0 0x400>;
5080 mboxes = <&apss_shared 0>;
5082 #clock-cells = <0>;
5095 reg = <0 0x0c3f0000 0 0x400>;
5100 reg = <0 0x0c440000 0 0x1100>,
5101 <0 0x0c600000 0 0x2000000>,
5102 <0 0x0e600000 0 0x100000>,
5103 <0 0x0e700000 0 0xa0000>,
5104 <0 0x0c40a000 0 0x26000>;
5108 qcom,ee = <0>;
5109 qcom,channel = <0>;
5111 #size-cells = <0>;
5118 reg = <0 0x14680000 0 0x40000>;
5123 ranges = <0 0 0x14680000 0x40000>;
5127 reg = <0x3f94c 0xc8>;
5133 reg = <0 0x15000000 0 0x80000>;
5205 reg = <0x0 0x150c5000 0x0 0x1000>;
5209 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5214 reg = <0x0 0x150c9000 0x0 0x1000>;
5218 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5223 reg = <0x0 0x150cd000 0x0 0x1000>;
5227 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5232 reg = <0x0 0x150d1000 0x0 0x1000>;
5236 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5241 reg = <0x0 0x150d5000 0x0 0x1000>;
5245 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5250 reg = <0x0 0x150d9000 0x0 0x1000>;
5253 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5258 reg = <0x0 0x150dd000 0x0 0x1000>;
5262 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5267 reg = <0x0 0x150e1000 0x0 0x1000>;
5272 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5277 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5285 reg = <0 0x17900000 0 0xd080>;
5292 reg = <0 0x17980000 0 0x1000>;
5294 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5299 reg = <0 0x17990000 0 0x1000>;
5306 reg = <0 0x179c0000 0 0x10000>,
5307 <0 0x179d0000 0 0x10000>,
5308 <0 0x179e0000 0 0x10000>;
5309 reg-names = "drv-0", "drv-1", "drv-2";
5313 qcom,tcs-offset = <0xd00>;
5390 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5391 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5398 reg = <0 0x17a40000 0 0x20000>;
5406 reg = <0 0x17184000 0 0x2a000>;
5412 iommus = <&apps_smmu 0x1806 0x0>;
5418 ranges = <0 0 0 0x20000000>;
5420 reg = <0 0x17c90000 0 0x1000>;
5423 frame-number = <0>;
5426 reg = <0x17ca0000 0x1000>,
5427 <0x17cb0000 0x1000>;
5433 reg = <0x17cc0000 0x1000>;
5440 reg = <0x17cd0000 0x1000>;
5447 reg = <0x17ce0000 0x1000>;
5454 reg = <0x17cf0000 0x1000>;
5461 reg = <0x17d00000 0x1000>;
5468 reg = <0x17d10000 0x1000>;
5475 reg = <0 0x17d41000 0 0x1400>;
5485 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5488 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5500 reg = <0 0x18800000 0 0x800000>;
5518 iommus = <&apps_smmu 0x0040 0x1>;
5737 thermal-sensors = <&tsens0 0>;
5855 thermal-sensors = <&tsens1 0>;
5970 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;