Lines Matching +full:0 +full:x146bf000
36 #clock-cells = <0>;
43 #clock-cells = <0>;
51 #size-cells = <0>;
56 reg = <0x0 0x100>;
76 reg = <0x0 0x101>;
91 reg = <0x0 0x102>;
106 reg = <0x0 0x103>;
118 cpu4: cpu@0 {
121 reg = <0x0 0x0>;
141 reg = <0x0 0x1>;
156 reg = <0x0 0x2>;
171 reg = <0x0 0x3>;
224 pwr_cpu_sleep_0: cpu-sleep-0-0 {
227 arm,psci-suspend-param = <0x40000002>;
233 pwr_cpu_sleep_1: cpu-sleep-0-1 {
236 arm,psci-suspend-param = <0x40000003>;
243 perf_cpu_sleep_0: cpu-sleep-1-0 {
246 arm,psci-suspend-param = <0x40000002>;
255 arm,psci-suspend-param = <0x40000003>;
262 pwr_cluster_sleep_0: cluster-sleep-0-0 {
265 arm,psci-suspend-param = <0x400000F2>;
272 pwr_cluster_sleep_1: cluster-sleep-0-1 {
275 arm,psci-suspend-param = <0x400000F3>;
282 pwr_cluster_sleep_2: cluster-sleep-0-2 {
285 arm,psci-suspend-param = <0x400000F4>;
292 perf_cluster_sleep_0: cluster-sleep-1-0 {
295 arm,psci-suspend-param = <0x400000F2>;
305 arm,psci-suspend-param = <0x400000F3>;
315 arm,psci-suspend-param = <0x400000F4>;
333 reg = <0x0 0x80000000 0x0 0x0>;
373 mboxes = <&apcs_glb 0>;
439 reg = <0x0 0x85600000 0x0 0x100000>;
444 reg = <0x0 0x85700000 0x0 0x100000>;
449 reg = <0x0 0x85800000 0x0 0x600000>;
455 reg = <0x0 0x85e00000 0x0 0x200000>;
463 reg = <0 0x86000000 0 0x200000>;
468 reg = <0x0 0x86200000 0x0 0x3300000>;
473 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
478 reg = <0x0 0x92a00000 0x0 0x1e00000>;
483 reg = <0x0 0x94800000 0x0 0x200000>;
488 reg = <0x0 0x94a00000 0x0 0x100000>;
493 reg = <0x0 0x9f800000 0x0 0x800000>;
498 reg = <0x0 0xf6000000 0x0 0x800000>;
503 reg = <0x0 0xf6800000 0x0 0x1400000>;
509 reg = <0x0 0xfed00000 0x0 0xa00000>;
514 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
515 size = <0x0 0x4000>;
531 qcom,local-pid = <0>;
551 qcom,local-pid = <0>;
566 soc@0 {
569 ranges = <0 0 0 0xffffffff>;
577 reg = <0x00100000 0x94000>;
586 reg = <0x00778000 0x7000>;
591 reg = <0x00780000 0x621c>;
596 reg = <0x243 0x1>;
601 reg = <0x41a2 0x1>;
608 reg = <0x00793000 0x1000>;
615 reg = <0x01008000 0x78000>;
621 reg = <0x010ac000 0x4>;
626 reg = <0x01500000 0x10000>;
632 reg = <0x01626000 0x7090>;
638 reg = <0x016c0000 0x40000>;
679 reg = <0x01704000 0xc100>;
695 reg = <0x01745000 0xa010>;
703 reg = <0x010ae000 0x1000>, /* TM */
704 <0x010ad000 0x1000>; /* SROT */
714 reg = <0x01f40000 0x20000>;
720 reg = <0x01f60000 0x20000>;
725 reg = <0x03100000 0x400000>,
726 <0x03500000 0x400000>,
727 <0x03900000 0x400000>;
731 gpio-ranges = <&tlmm 0 0 114>;
1020 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1024 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1053 qcom,smem-states = <&modem_smp2p_out 0>;
1059 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1080 reg = <0x05000000 0x40000>;
1100 iommus = <&kgsl_smmu 0>;
1119 opp-supported-hw = <0xa2>;
1125 opp-supported-hw = <0xff>;
1131 opp-supported-hw = <0xff>;
1137 opp-supported-hw = <0xff>;
1143 opp-supported-hw = <0xff>;
1149 opp-supported-hw = <0xff>;
1155 opp-supported-hw = <0xff>;
1167 reg = <0x05040000 0x10000>;
1205 reg = <0x05065000 0x9038>;
1217 reg = <0x05100000 0x40000>;
1246 reg = <0x00290000 0x10000>;
1251 reg = <0x0800f000 0x1000>,
1252 <0x08400000 0x1000000>,
1253 <0x09400000 0x1000000>,
1254 <0x0a400000 0x220000>,
1255 <0x0800a000 0x3000>;
1259 qcom,ee = <0>;
1260 qcom,channel = <0>;
1262 #size-cells = <0>;
1269 reg = <0x0a8f8800 0x400>;
1305 reg = <0x0a800000 0xc8d0>;
1315 snps,hird-threshold = /bits/ 8 <0>;
1321 reg = <0x0c010000 0x1000>;
1332 #clock-cells = <0>;
1333 #phy-cells = <0>;
1340 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
1347 reg = <0x0c012000 0x180>;
1348 #phy-cells = <0>;
1361 reg = <0x0c014000 0x180>;
1362 #phy-cells = <0>;
1375 reg = <0x0c084000 0x1000>;
1392 <&gnoc 0 &cnoc 28>;
1397 pinctrl-0 = <&sdc2_state_on>;
1429 reg = <0x0c0c4000 0x1000>,
1430 <0x0c0c5000 0x1000>,
1431 <0x0c0c8000 0x8000>;
1447 <&gnoc 0 &cnoc 27>;
1451 pinctrl-0 = <&sdc1_state_on>;
1486 reg = <0x0c2f8800 0x400>;
1516 reg = <0x0c200000 0xc8d0>;
1527 snps,hird-threshold = /bits/ 8 <0>;
1533 reg = <0x0c8c0000 0x40000>;
1553 <0>,
1554 <0>,
1555 <0>,
1556 <0>;
1561 reg = <0x0c900000 0x1000>,
1562 <0x0c9b0000 0x1040>;
1588 reg = <0x0c901000 0x89000>;
1592 interrupts = <0>;
1609 <&gnoc 0 &mnoc 17>;
1613 iommus = <&mmss_smmu 0>;
1619 #size-cells = <0>;
1621 port@0 {
1622 reg = <0>;
1663 reg = <0x0c994000 0x400>;
1702 #size-cells = <0>;
1704 port@0 {
1705 reg = <0>;
1721 reg = <0x0c994400 0x100>,
1722 <0x0c994500 0x300>,
1723 <0x0c994800 0x188>;
1729 #phy-cells = <0>;
1739 reg = <0x0c144000 0x1f000>;
1744 qcom,ee = <0>;
1752 reg = <0x0c16f000 0x200>;
1757 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1760 pinctrl-0 = <&blsp1_uart1_default>;
1767 reg = <0x0c170000 0x1000>;
1775 pinctrl-0 = <&blsp1_uart2_default>;
1781 reg = <0x0c175000 0x600>;
1792 pinctrl-0 = <&i2c1_default>;
1795 #size-cells = <0>;
1801 reg = <0x0c176000 0x600>;
1812 pinctrl-0 = <&i2c2_default>;
1815 #size-cells = <0>;
1821 reg = <0x0c177000 0x600>;
1832 pinctrl-0 = <&i2c3_default>;
1835 #size-cells = <0>;
1841 reg = <0x0c178000 0x600>;
1852 pinctrl-0 = <&i2c4_default>;
1855 #size-cells = <0>;
1861 reg = <0x0c184000 0x1f000>;
1866 qcom,ee = <0>;
1874 reg = <0x0c1af000 0x200>;
1879 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1882 pinctrl-0 = <&blsp2_uart1_default>;
1889 reg = <0x0c1b5000 0x600>;
1900 pinctrl-0 = <&i2c5_default>;
1903 #size-cells = <0>;
1909 reg = <0x0c1b6000 0x600>;
1920 pinctrl-0 = <&i2c6_default>;
1923 #size-cells = <0>;
1929 reg = <0x0c1b7000 0x600>;
1940 pinctrl-0 = <&i2c7_default>;
1943 #size-cells = <0>;
1949 reg = <0x0c1b8000 0x600>;
1960 pinctrl-0 = <&i2c8_default>;
1963 #size-cells = <0>;
1969 reg = <0x146bf000 0x1000>;
1974 ranges = <0 0x146bf000 0x1000>;
1978 reg = <0x94c 0xc8>;
1984 reg = <0x0ca00020 0x10>,
1985 <0x0ca30000 0x100>,
1986 <0x0ca30400 0x100>,
1987 <0x0ca30800 0x100>,
1988 <0x0ca30c00 0x100>,
1989 <0x0c824000 0x1000>,
1990 <0x0ca00120 0x4>,
1991 <0x0c825000 0x1000>,
1992 <0x0ca00124 0x4>,
1993 <0x0c826000 0x1000>,
1994 <0x0ca00128 0x4>,
1995 <0x0ca31000 0x500>,
1996 <0x0ca10000 0x1000>,
1997 <0x0ca14000 0x1000>;
2118 iommus = <&mmss_smmu 0xc00>,
2119 <&mmss_smmu 0xc01>,
2120 <&mmss_smmu 0xc02>,
2121 <&mmss_smmu 0xc03>;
2128 #size-cells = <0>;
2135 #size-cells = <0>;
2136 reg = <0x0ca0c000 0x1000>;
2152 pinctrl-0 = <&cci0_default &cci1_default>;
2156 cci_i2c0: i2c-bus@0 {
2157 reg = <0>;
2160 #size-cells = <0>;
2167 #size-cells = <0>;
2173 reg = <0x0cc00000 0xff000>;
2179 interconnects = <&gnoc 0 &mnoc 13>,
2183 iommus = <&mmss_smmu 0x400>,
2184 <&mmss_smmu 0x401>,
2185 <&mmss_smmu 0x40a>,
2186 <&mmss_smmu 0x407>,
2187 <&mmss_smmu 0x40e>,
2188 <&mmss_smmu 0x40f>,
2189 <&mmss_smmu 0x408>,
2190 <&mmss_smmu 0x409>,
2191 <&mmss_smmu 0x40b>,
2192 <&mmss_smmu 0x40c>,
2193 <&mmss_smmu 0x40d>,
2194 <&mmss_smmu 0x410>,
2195 <&mmss_smmu 0x421>,
2196 <&mmss_smmu 0x428>,
2197 <&mmss_smmu 0x429>,
2198 <&mmss_smmu 0x42b>,
2199 <&mmss_smmu 0x42c>,
2200 <&mmss_smmu 0x42d>,
2201 <&mmss_smmu 0x411>,
2202 <&mmss_smmu 0x431>;
2224 reg = <0x0cd00000 0x40000>;
2268 reg = <0x15700000 0x4040>;
2272 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2286 qcom,smem-states = <&adsp_smp2p_out 0>;
2301 #size-cells = <0>;
2314 #size-cells = <0>;
2325 #size-cells = <0>;
2336 #sound-dai-cells = <0>;
2345 reg = <0x17900000 0xe000>;
2352 reg = <0x17911000 0x1000>;
2362 reg = <0x17920000 0x1000>;
2366 frame-number = <0>;
2369 reg = <0x17921000 0x1000>,
2370 <0x17922000 0x1000>;
2376 reg = <0x17923000 0x1000>;
2383 reg = <0x17924000 0x1000>;
2390 reg = <0x17925000 0x1000>;
2397 reg = <0x17926000 0x1000>;
2404 reg = <0x17927000 0x1000>;
2411 reg = <0x17928000 0x1000>;
2418 reg = <0x17a00000 0x10000>, /* GICD */
2419 <0x17b00000 0x100000>; /* GICR * 8 */
2426 redistributor-stride = <0x0 0x20000>;
2432 reg = <0x18800000 0x800000>;
2450 iommus = <&anoc2_smmu 0x1a00>,
2451 <&anoc2_smmu 0x1a01>;
2465 thermal-sensors = <&tsens 0>;
2649 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;