Lines Matching +full:0 +full:x63000000
67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
137 reg = <0x0 0x200>;
138 clocks = <&cpufreq_hw 0>;
149 qcom,freq-domain = <&cpufreq_hw 0>;
161 reg = <0x0 0x300>;
162 clocks = <&cpufreq_hw 0>;
173 qcom,freq-domain = <&cpufreq_hw 0>;
185 reg = <0x0 0x400>;
186 clocks = <&cpufreq_hw 0>;
197 qcom,freq-domain = <&cpufreq_hw 0>;
209 reg = <0x0 0x500>;
210 clocks = <&cpufreq_hw 0>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
233 reg = <0x0 0x600>;
257 reg = <0x0 0x700>;
317 little_cpu_sleep_0: cpu-sleep-0-0 {
320 arm,psci-suspend-param = <0x40000003>;
327 little_cpu_sleep_1: cpu-sleep-0-1 {
330 arm,psci-suspend-param = <0x40000004>;
337 big_cpu_sleep_0: cpu-sleep-1-0 {
340 arm,psci-suspend-param = <0x40000003>;
350 arm,psci-suspend-param = <0x40000004>;
359 cluster_sleep_pc: cluster-sleep-0 {
361 arm,psci-suspend-param = <0x41000044>;
369 arm,psci-suspend-param = <0x41001244>;
377 arm,psci-suspend-param = <0x4100b244>;
394 reg = <0 0x80000000 0 0>;
585 #power-domain-cells = <0>;
591 #power-domain-cells = <0>;
597 #power-domain-cells = <0>;
603 #power-domain-cells = <0>;
609 #power-domain-cells = <0>;
615 #power-domain-cells = <0>;
621 #power-domain-cells = <0>;
627 #power-domain-cells = <0>;
633 #power-domain-cells = <0>;
646 reg = <0x0 0x80000000 0x0 0x600000>;
651 reg = <0x0 0x80600000 0x0 0x200000>;
656 reg = <0x0 0x80800000 0x0 0x20000>;
661 reg = <0x0 0x80820000 0x0 0x20000>;
667 reg = <0x0 0x808ff000 0x0 0x1000>;
672 reg = <0x0 0x80900000 0x0 0x200000>;
677 reg = <0x0 0x80b00000 0x0 0x3900000>;
682 reg = <0 0x8b700000 0 0x10000>;
688 reg = <0x0 0x94600000 0x0 0x200000>;
710 qcom,local-pid = <0>;
734 qcom,local-pid = <0>;
755 qcom,local-pid = <0>;
781 soc: soc@0 {
784 ranges = <0 0 0 0 0x10 0>;
785 dma-ranges = <0 0 0 0 0x10 0>;
790 reg = <0 0x00100000 0 0x1f0000>;
803 reg = <0 0x00784000 0 0x7a0>,
804 <0 0x00780000 0 0x7a0>,
805 <0 0x00782000 0 0x100>,
806 <0 0x00786000 0 0x1fff>;
814 reg = <0x25b 0x1>;
819 reg = <0x1d2 0x2>;
826 reg = <0 0x007c4000 0 0x1000>,
827 <0 0x007c5000 0 0x1000>;
830 iommus = <&apps_smmu 0x60 0x0>;
839 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
863 opp-avg-kBps = <100000 0>;
870 opp-avg-kBps = <390000 0>;
877 reg = <0 0x008c0000 0 0x6000>;
884 iommus = <&apps_smmu 0x43 0x0>;
889 reg = <0 0x00880000 0 0x4000>;
893 pinctrl-0 = <&qup_i2c0_default>;
896 #size-cells = <0>;
897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
909 reg = <0 0x00880000 0 0x4000>;
913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
916 #size-cells = <0>;
919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
927 reg = <0 0x00880000 0 0x4000>;
931 pinctrl-0 = <&qup_uart0_default>;
935 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
943 reg = <0 0x00884000 0 0x4000>;
947 pinctrl-0 = <&qup_i2c1_default>;
950 #size-cells = <0>;
951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
953 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
963 reg = <0 0x00884000 0 0x4000>;
967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
970 #size-cells = <0>;
973 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
981 reg = <0 0x00884000 0 0x4000>;
985 pinctrl-0 = <&qup_uart1_default>;
989 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
997 reg = <0 0x00888000 0 0x4000>;
1001 pinctrl-0 = <&qup_i2c2_default>;
1004 #size-cells = <0>;
1005 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1017 reg = <0 0x00888000 0 0x4000>;
1021 pinctrl-0 = <&qup_uart2_default>;
1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1026 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1033 reg = <0 0x0088c000 0 0x4000>;
1037 pinctrl-0 = <&qup_i2c3_default>;
1040 #size-cells = <0>;
1041 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1042 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1043 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1053 reg = <0 0x0088c000 0 0x4000>;
1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060 #size-cells = <0>;
1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1071 reg = <0 0x0088c000 0 0x4000>;
1075 pinctrl-0 = <&qup_uart3_default>;
1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1087 reg = <0 0x00890000 0 0x4000>;
1091 pinctrl-0 = <&qup_i2c4_default>;
1094 #size-cells = <0>;
1095 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1097 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1107 reg = <0 0x00890000 0 0x4000>;
1111 pinctrl-0 = <&qup_uart4_default>;
1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1123 reg = <0 0x00894000 0 0x4000>;
1127 pinctrl-0 = <&qup_i2c5_default>;
1130 #size-cells = <0>;
1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1133 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1143 reg = <0 0x00894000 0 0x4000>;
1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150 #size-cells = <0>;
1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1161 reg = <0 0x00894000 0 0x4000>;
1165 pinctrl-0 = <&qup_uart5_default>;
1169 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1178 reg = <0 0x00ac0000 0 0x6000>;
1185 iommus = <&apps_smmu 0x4c3 0x0>;
1190 reg = <0 0x00a80000 0 0x4000>;
1194 pinctrl-0 = <&qup_i2c6_default>;
1197 #size-cells = <0>;
1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1200 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1210 reg = <0 0x00a80000 0 0x4000>;
1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217 #size-cells = <0>;
1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1228 reg = <0 0x00a80000 0 0x4000>;
1232 pinctrl-0 = <&qup_uart6_default>;
1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1244 reg = <0 0x00a84000 0 0x4000>;
1248 pinctrl-0 = <&qup_i2c7_default>;
1251 #size-cells = <0>;
1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1254 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1264 reg = <0 0x00a84000 0 0x4000>;
1268 pinctrl-0 = <&qup_uart7_default>;
1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1280 reg = <0 0x00a88000 0 0x4000>;
1284 pinctrl-0 = <&qup_i2c8_default>;
1287 #size-cells = <0>;
1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1300 reg = <0 0x00a88000 0 0x4000>;
1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307 #size-cells = <0>;
1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1311 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1318 reg = <0 0x00a88000 0 0x4000>;
1322 pinctrl-0 = <&qup_uart8_default>;
1326 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1327 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1334 reg = <0 0x00a8c000 0 0x4000>;
1338 pinctrl-0 = <&qup_i2c9_default>;
1341 #size-cells = <0>;
1342 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1344 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1354 reg = <0 0x00a8c000 0 0x4000>;
1358 pinctrl-0 = <&qup_uart9_default>;
1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1370 reg = <0 0x00a90000 0 0x4000>;
1374 pinctrl-0 = <&qup_i2c10_default>;
1377 #size-cells = <0>;
1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1380 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1390 reg = <0 0x00a90000 0 0x4000>;
1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397 #size-cells = <0>;
1400 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1408 reg = <0 0x00a90000 0 0x4000>;
1412 pinctrl-0 = <&qup_uart10_default>;
1416 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1424 reg = <0 0x00a94000 0 0x4000>;
1428 pinctrl-0 = <&qup_i2c11_default>;
1431 #size-cells = <0>;
1432 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1434 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1444 reg = <0 0x00a94000 0 0x4000>;
1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451 #size-cells = <0>;
1454 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1462 reg = <0 0x00a94000 0 0x4000>;
1466 pinctrl-0 = <&qup_uart11_default>;
1470 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1471 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1479 reg = <0 0x01500000 0 0x28000>;
1486 reg = <0 0x01620000 0 0x17080>;
1493 reg = <0 0x01638000 0 0x1000>;
1500 reg = <0 0x01650000 0 0x1000>;
1507 reg = <0 0x016e0000 0 0x15080>;
1514 reg = <0 0x01705000 0 0x9000>;
1521 reg = <0 0x0170e000 0 0x6000>;
1528 reg = <0 0x01740000 0 0x1c100>;
1536 reg = <0 0x01d84000 0 0x3000>;
1547 iommus = <&apps_smmu 0xa0 0x0>;
1564 <0 0>,
1565 <0 0>,
1567 <0 0>,
1568 <0 0>,
1569 <0 0>;
1584 reg = <0 0x01d87000 0 0x1000>;
1592 resets = <&ufs_mem_hc 0>;
1594 #phy-cells = <0>;
1601 reg = <0 0x01d90000 0 0x8000>;
1608 iommus = <&apps_smmu 0x440 0x0>,
1609 <&apps_smmu 0x442 0x0>;
1610 reg = <0 0x01e40000 0 0x7000>,
1611 <0 0x01e47000 0 0x2000>,
1612 <0 0x01e04000 0 0x2c000>;
1619 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1629 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1630 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1631 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1638 qcom,smem-states = <&ipa_smp2p_out 0>,
1648 reg = <0 0x01f40000 0 0x20000>;
1654 reg = <0 0x01f60000 0 0x20000>;
1659 reg = <0 0x01fc0000 0 0x40000>;
1664 reg = <0 0x03500000 0 0x300000>,
1665 <0 0x03900000 0 0x300000>,
1666 <0 0x03d00000 0 0x300000>;
1673 gpio-ranges = <&tlmm 0 0 120>;
2128 reg = <0 0x04080000 0 0x4040>;
2131 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2151 qcom,smem-states = <&modem_smp2p_out 0>;
2166 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2167 <0 0x05061000 0 0x800>;
2170 iommus = <&adreno_smmu 0>;
2179 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2189 opp-supported-hw = <0x04>;
2196 opp-supported-hw = <0x07>;
2203 opp-supported-hw = <0x07>;
2210 opp-supported-hw = <0x07>;
2217 opp-supported-hw = <0x07>;
2224 opp-supported-hw = <0x07>;
2231 opp-supported-hw = <0x07>;
2238 opp-supported-hw = <0x07>;
2245 reg = <0 0x05040000 0 0x10000>;
2268 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2269 <0 0x0b490000 0 0x10000>;
2296 reg = <0 0x05090000 0 0x9000>;
2310 reg = <0x0 0x010a2000 0x0 0x1000>,
2311 <0x0 0x010ae000 0x0 0x2000>;
2317 reg = <0 0x06002000 0 0x1000>,
2318 <0 0x16280000 0 0x180000>;
2335 reg = <0 0x06041000 0 0x1000>;
2350 #size-cells = <0>;
2363 reg = <0 0x06042000 0 0x1000>;
2378 #size-cells = <0>;
2391 reg = <0 0x06045000 0 0x1000>;
2406 #size-cells = <0>;
2408 port@0 {
2409 reg = <0>;
2426 reg = <0 0x06046000 0 0x1000>;
2450 reg = <0 0x06048000 0 0x1000>;
2451 iommus = <&apps_smmu 0x04a0 0x20>;
2468 reg = <0 0x06b04000 0 0x1000>;
2483 #size-cells = <0>;
2496 reg = <0 0x06b05000 0 0x1000>;
2520 reg = <0 0x06b06000 0 0x1000>;
2545 reg = <0 0x07040000 0 0x1000>;
2565 reg = <0 0x07140000 0 0x1000>;
2585 reg = <0 0x07240000 0 0x1000>;
2605 reg = <0 0x07340000 0 0x1000>;
2625 reg = <0 0x07440000 0 0x1000>;
2645 reg = <0 0x07540000 0 0x1000>;
2665 reg = <0 0x07640000 0 0x1000>;
2685 reg = <0 0x07740000 0 0x1000>;
2705 reg = <0 0x07800000 0 0x1000>;
2720 #size-cells = <0>;
2722 port@0 {
2723 reg = <0>;
2782 reg = <0 0x07810000 0 0x1000>;
2806 reg = <0 0x08804000 0 0x1000>;
2808 iommus = <&apps_smmu 0x80 0>;
2818 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2819 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2835 opp-avg-kBps = <100000 0>;
2842 opp-avg-kBps = <200000 0>;
2849 reg = <0 0x088dc000 0 0x600>;
2850 iommus = <&apps_smmu 0x20 0x0>;
2852 #size-cells = <0>;
2857 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2858 &config_noc SLAVE_QSPI_0 0>;
2867 reg = <0 0x088e3000 0 0x400>;
2869 #phy-cells = <0>;
2880 reg = <0 0x088e8000 0 0x3000>;
2904 reg = <0 0x090b6300 0 0x600>;
2914 opp-0 {
2942 reg = <0 0x090cd000 0 0x1000>;
2952 opp-0 {
2988 reg = <0 0x09160000 0 0x03200>;
2995 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
3002 reg = <0 0x09680000 0 0x3e200>;
3009 reg = <0 0x09990000 0 0x1600>;
3016 reg = <0 0x0a6f8800 0 0x400>;
3054 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
3055 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
3062 reg = <0 0x0a600000 0 0xe000>;
3064 iommus = <&apps_smmu 0x540 0>;
3078 reg = <0 0x0aa00000 0 0xff000>;
3092 iommus = <&apps_smmu 0x0c00 0x60>;
3094 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3138 reg = <0 0x0ab00000 0 0x10000>;
3148 reg = <0 0x0ac00000 0 0x1000>;
3155 reg = <0 0x0ad00000 0 0x10000>;
3167 reg = <0 0x0ae00000 0 0x1000>;
3188 iommus = <&apps_smmu 0x800 0x2>;
3198 reg = <0 0x0ae01000 0 0x8f000>,
3199 <0 0x0aeb0000 0 0x3000>;
3220 interrupts = <0>;
3224 #size-cells = <0>;
3226 port@0 {
3227 reg = <0>;
3269 reg = <0 0x0ae94000 0 0x400>;
3299 #size-cells = <0>;
3305 #size-cells = <0>;
3307 port@0 {
3308 reg = <0>;
3343 reg = <0 0x0ae94400 0 0x200>,
3344 <0 0x0ae94600 0 0x280>,
3345 <0 0x0ae94a00 0 0x1e0>;
3351 #phy-cells = <0>;
3364 reg = <0 0x0ae90000 0 0x200>,
3365 <0 0x0ae90200 0 0x200>,
3366 <0 0x0ae90400 0 0xc00>,
3367 <0 0x0ae91000 0 0x400>,
3368 <0 0x0ae91400 0 0x400>;
3390 #sound-dai-cells = <0>;
3394 #size-cells = <0>;
3395 port@0 {
3396 reg = <0>;
3436 reg = <0 0x0af00000 0 0x200000>;
3456 reg = <0 0x0b220000 0 0x30000>;
3457 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3465 reg = <0 0x0b2e0000 0 0x20000>;
3471 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3472 <0 0x0c222000 0 0x1ff>; /* SROT */
3482 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3483 <0 0x0c223000 0 0x1ff>; /* SROT */
3493 reg = <0 0x0c2a0000 0 0x31000>;
3499 reg = <0 0x0c300000 0 0x400>;
3501 mboxes = <&apss_shared 0>;
3503 #clock-cells = <0>;
3508 reg = <0 0x0c3f0000 0 0x400>;
3513 reg = <0 0x0c440000 0 0x1100>,
3514 <0 0x0c600000 0 0x2000000>,
3515 <0 0x0e600000 0 0x100000>,
3516 <0 0x0e700000 0 0xa0000>,
3517 <0 0x0c40a000 0 0x26000>;
3521 qcom,ee = <0>;
3522 qcom,channel = <0>;
3524 #size-cells = <0>;
3531 reg = <0 0x14680000 0 0x2e000>;
3536 ranges = <0 0 0x14680000 0x2e000>;
3540 reg = <0x2a94c 0xc8>;
3546 reg = <0 0x15000000 0 0x100000>;
3640 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3641 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3648 reg = <0 0x17a40000 0 0x20000>;
3656 reg = <0 0x17c00000 0 0x10000>;
3662 reg = <0 0x17c10000 0 0x1000>;
3664 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3670 ranges = <0 0 0 0x20000000>;
3672 reg = <0 0x17c20000 0 0x1000>;
3675 frame-number = <0>;
3678 reg = <0x17c21000 0x1000>,
3679 <0x17c22000 0x1000>;
3685 reg = <0x17c23000 0x1000>;
3692 reg = <0x17c25000 0x1000>;
3699 reg = <0x17c27000 0x1000>;
3706 reg = <0x17c29000 0x1000>;
3713 reg = <0x17c2b000 0x1000>;
3720 reg = <0x17c2d000 0x1000>;
3727 reg = <0 0x18200000 0 0x10000>,
3728 <0 0x18210000 0 0x10000>,
3729 <0 0x18220000 0 0x10000>;
3730 reg-names = "drv-0", "drv-1", "drv-2";
3734 qcom,tcs-offset = <0xd00>;
3810 reg = <0 0x18321000 0 0x1400>;
3820 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3832 reg = <0 0x18800000 0 0x800000>;
3834 iommus = <&apps_smmu 0xc0 0x1>;
3855 reg = <0 0x62400000 0 0x100>;
3858 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3876 qcom,smem-states = <&adsp_smp2p_out 0>;
3892 #size-cells = <0>;
3908 #size-cells = <0>;
3926 #size-cells = <0>;
3928 iommus = <&apps_smmu 0x1001 0x0>;
3939 #sound-dai-cells = <0>;
3949 #size-cells = <0>;
3954 iommus = <&apps_smmu 0x1003 0x0>;
3960 iommus = <&apps_smmu 0x1004 0x0>;
3966 iommus = <&apps_smmu 0x1005 0x0>;
3975 reg = <0 0x62d00000 0 0x50000>,
3976 <0 0x62780000 0 0x30000>;
3991 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3994 iommus = <&apps_smmu 0x1020 0>,
3995 <&apps_smmu 0x1021 0>,
3996 <&apps_smmu 0x1032 0>;
4017 #size-cells = <0>;
4026 reg = <0 0x63000000 0 0x28>;
4491 thermal-sensors = <&tsens0 0>;
4603 thermal-sensors = <&tsens1 0>;
4806 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;