Lines Matching +full:0 +full:xae91000
34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0x0 0x200>;
99 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0x0 0x300>;
119 clocks = <&cpufreq_hw 0>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
158 cpu_sleep_0: cpu-sleep-0-0 {
161 arm,psci-suspend-param = <0x40000003>;
168 cpu_sleep_1: cpu-sleep-0-1 {
171 arm,psci-suspend-param = <0x40000004>;
180 cluster_sleep_0: cluster-sleep-0 {
182 arm,psci-suspend-param = <0x41000044>;
190 arm,psci-suspend-param = <0x41002344>;
198 arm,psci-suspend-param = <0x4100c344>;
209 qcom,dload-mode = <&tcsr_mutex 0x13000>;
215 clk_virt: interconnect-0 {
230 reg = <0x0 0x80000000 0x0 0x0>;
243 #power-domain-cells = <0>;
249 #power-domain-cells = <0>;
255 #power-domain-cells = <0>;
261 #power-domain-cells = <0>;
267 #power-domain-cells = <0>;
278 reg = <0x0 0x80000000 0x0 0x600000>;
283 reg = <0x0 0x80600000 0x0 0x40000>;
288 reg = <0x0 0x80640000 0x0 0x1c0000>;
293 reg = <0x0 0x80800000 0x0 0x60000>;
299 reg = <0x0 0x80860000 0x0 0x20000>;
304 reg = <0x0 0x80880000 0x0 0x20000>;
309 reg = <0x0 0x808a0000 0x0 0x40000>;
314 reg = <0x0 0x808e0000 0x0 0x4000>;
319 reg = <0x0 0x808e4000 0x0 0x10000>;
324 reg = <0x0 0x808ff000 0x0 0x1000>;
330 reg = <0x0 0x80900000 0x0 0x200000>;
336 reg = <0x0 0x80b00000 0x0 0x100000>;
341 reg = <0x0 0x80c00000 0x0 0xe00000>;
346 reg = <0x0 0x84e00000 0x0 0x800000>;
351 reg = <0x0 0x86f00000 0x0 0x500000>;
356 reg = <0x0 0x87600000 0x0 0x1e00000>;
361 reg = <0x0 0x89400000 0x0 0xf00000>;
366 reg = <0x0 0x8a300000 0x0 0x10000>;
371 reg = <0x0 0x8a310000 0x0 0xa000>;
376 reg = <0x0 0x8a31a000 0x0 0x2000>;
381 reg = <0x0 0x8a400000 0x0 0x700000>;
387 reg = <0x0 0xa6e00000 0x0 0x40000>;
392 reg = <0x0 0xa6f00000 0x0 0x100000>;
397 reg = <0x0 0xe8800000 0x0 0x100000>;
402 reg = <0x0 0xe8900000 0x0 0x500000>;
407 reg = <0x0 0xe8e00000 0x0 0x500000>;
412 reg = <0x0 0xe9300000 0x0 0xc00000>;
425 qcom,local-pid = <0>;
449 qcom,local-pid = <0>;
464 soc: soc@0 {
468 ranges = <0 0 0 0 0x10 0>;
469 dma-ranges = <0 0 0 0 0x10 0>;
473 reg = <0x0 0x00100000 0x0 0x1f4200>;
486 reg = <0x0 0x007c4000 0x0 0x1000>,
487 <0x0 0x007c5000 0x0 0x1000>;
490 iommus = <&apps_smmu 0x160 0x0>;
507 pinctrl-0 = <&sdc1_default>;
529 opp-avg-kBps = <104000 0>;
536 opp-avg-kBps = <400000 0>;
543 reg = <0x0 0x00900000 0x0 0x60000>;
558 dma-channel-mask = <0x7e>;
559 iommus = <&apps_smmu 0x76 0x0>;
566 reg = <0x0 0x009c0000 0x0 0x2000>;
570 iommus = <&apps_smmu 0x63 0x0>;
582 reg = <0x0 0x00980000 0x0 0x4000>;
585 pinctrl-0 = <&qup_i2c0_data_clk>;
589 #size-cells = <0>;
597 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
598 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
606 reg = <0x0 0x00980000 0x0 0x4000>;
610 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
619 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
620 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
623 #size-cells = <0>;
630 reg = <0x0 0x00984000 0x0 0x4000>;
633 pinctrl-0 = <&qup_i2c1_data_clk>;
637 #size-cells = <0>;
645 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
654 reg = <0x0 0x00984000 0x0 0x4000>;
658 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
667 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
671 #size-cells = <0>;
678 reg = <0x0 0x00988000 0x0 0x4000>;
681 pinctrl-0 = <&qup_i2c2_data_clk>;
685 #size-cells = <0>;
693 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
702 reg = <0x0 0x00988000 0x0 0x4000>;
706 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
715 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
719 #size-cells = <0>;
727 reg = <0x0 0x0098c000 0x0 0x4000>;
730 pinctrl-0 = <&qup_i2c3_data_clk>;
734 #size-cells = <0>;
742 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
751 reg = <0x0 0x0098c000 0x0 0x4000>;
755 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
764 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
768 #size-cells = <0>;
775 reg = <0x0 0x00990000 0x0 0x4000>;
778 pinctrl-0 = <&qup_i2c4_data_clk>;
782 #size-cells = <0>;
790 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
799 reg = <0x0 0x00990000 0x0 0x4000>;
803 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
812 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
816 #size-cells = <0>;
823 reg = <0x0 0x00994000 0x0 0x4000>;
826 pinctrl-0 = <&qup_i2c5_data_clk>;
830 #size-cells = <0>;
838 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
847 reg = <0x0 0x00994000 0x0 0x4000>;
851 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
860 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
864 #size-cells = <0>;
873 reg = <0x0 0x00a00000 0x0 0x60000>;
887 dma-channel-mask = <0x7e>;
888 iommus = <&apps_smmu 0x16 0x0>;
895 reg = <0x0 0x00ac0000 0x0 0x6000>;
899 iommus = <&apps_smmu 0x3 0x0>;
911 reg = <0x0 0x00a80000 0x0 0x4000>;
914 pinctrl-0 = <&qup_i2c6_data_clk>;
918 #size-cells = <0>;
926 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
927 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
935 reg = <0x0 0x00a80000 0x0 0x4000>;
939 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
948 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
949 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
952 #size-cells = <0>;
959 reg = <0x0 0x00a84000 0x0 0x4000>;
962 pinctrl-0 = <&qup_i2c7_data_clk>;
966 #size-cells = <0>;
974 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
983 reg = <0x0 0x00a84000 0x0 0x4000>;
987 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
996 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1000 #size-cells = <0>;
1007 reg = <0x0 0x00a84000 0x0 0x4000>;
1010 pinctrl-0 = <&qup_uart7_default>;
1024 reg = <0x0 0x00a88000 0x0 0x4000>;
1027 pinctrl-0 = <&qup_i2c8_data_clk>;
1031 #size-cells = <0>;
1039 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1048 reg = <0x0 0x00a88000 0x0 0x4000>;
1052 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1061 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1065 #size-cells = <0>;
1072 reg = <0x0 0x00a8c000 0x0 0x4000>;
1075 pinctrl-0 = <&qup_i2c9_data_clk>;
1079 #size-cells = <0>;
1087 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1096 reg = <0x0 0x00a8c000 0x0 0x4000>;
1100 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1109 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1113 #size-cells = <0>;
1120 reg = <0x0 0x00a90000 0x0 0x4000>;
1123 pinctrl-0 = <&qup_i2c10_data_clk>;
1127 #size-cells = <0>;
1135 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1144 reg = <0x0 0x00a90000 0x0 0x4000>;
1148 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1157 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1161 #size-cells = <0>;
1168 reg = <0x0 0x00a94000 0x0 0x4000>;
1171 pinctrl-0 = <&qup_i2c11_data_clk>;
1175 #size-cells = <0>;
1183 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1192 reg = <0x0 0x00a94000 0x0 0x4000>;
1196 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1205 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1209 #size-cells = <0>;
1216 reg = <0x0 0x00a94000 0x0 0x4000>;
1219 pinctrl-0 = <&qup_uart11_default>;
1235 reg = <0x0 0x01500000 0x0 0x10>;
1242 reg = <0x0 0x01680000 0x0 0x29080>;
1250 reg = <0x0 0x016c0000 0x0 0xa080>;
1259 reg = <0x0 0x01740000 0x0 0x1f100>;
1267 reg = <0x0 0x01c00000 0x0 0x3000>,
1268 <0x0 0x60000000 0x0 0xf1d>,
1269 <0x0 0x60000f20 0x0 0xa8>,
1270 <0x0 0x60001000 0x0 0x1000>,
1271 <0x0 0x60100000 0x0 0x100000>,
1272 <0x0 0x01c0c000 0x0 0x1000>;
1276 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1277 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1278 bus-range = <0x00 0xff>;
1282 linux,pci-domain = <0>;
1304 interrupt-map-mask = <0 0 0 0x7>;
1305 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1306 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1307 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1308 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1331 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1332 <0x100 &apps_smmu 0x1c01 0x1>;
1344 pcieport0: pcie@0 {
1346 reg = <0x0 0x0 0x0 0x0 0x0>;
1347 bus-range = <0x01 0xff>;
1357 reg = <0x0 0x01c06000 0x0 0x2000>;
1375 #clock-cells = <0>;
1378 #phy-cells = <0>;
1386 reg = <0x0 0x01c08000 0x0 0x3000>,
1387 <0x0 0x40000000 0x0 0xf1d>,
1388 <0x0 0x40000f20 0x0 0xa8>,
1389 <0x0 0x40001000 0x0 0x1000>,
1390 <0x0 0x40100000 0x0 0x100000>,
1391 <0x0 0x01c0b000 0x0 0x1000>;
1395 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1396 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1397 bus-range = <0x00 0xff>;
1423 interrupt-map-mask = <0 0 0 0x7>;
1424 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1425 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1426 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1427 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1457 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1458 <0x100 &apps_smmu 0x1e01 0x1>;
1471 pcie@0 {
1473 reg = <0x0 0x0 0x0 0x0 0x0>;
1474 bus-range = <0x01 0xff>;
1484 reg = <0x0 0x01c08000 0x0 0x3000>,
1485 <0x0 0x40000000 0x0 0xf1d>,
1486 <0x0 0x40000f20 0x0 0xa8>,
1487 <0x0 0x40001000 0x0 0x1000>,
1488 <0x0 0x40200000 0x0 0x1000000>,
1489 <0x0 0x01c0b000 0x0 0x1000>,
1490 <0x0 0x40002000 0x0 0x2000>;
1531 iommus = <&apps_smmu 0x1e00 0x1>;
1545 reg = <0x0 0x01c0e000 0x0 0x2000>;
1563 #clock-cells = <0>;
1566 #phy-cells = <0>;
1573 reg = <0x0 0x01f40000 0x0 0x20000>;
1580 reg = <0x0 0x01fc0000 0x0 0x30000>;
1588 reg = <0x0 0x03000000 0x0 0x10000>;
1591 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1609 qcom,smem-states = <&smp2p_adsp_out 0>;
1630 #size-cells = <0>;
1635 #sound-dai-cells = <0>;
1641 iommus = <&apps_smmu 0x1801 0x0>;
1669 #size-cells = <0>;
1674 iommus = <&apps_smmu 0x1803 0x0>;
1680 iommus = <&apps_smmu 0x1804 0x0>;
1686 iommus = <&apps_smmu 0x1805 0x0>;
1692 iommus = <&apps_smmu 0x1806 0x0>;
1700 reg = <0x0 0x03d00000 0x0 0x40000>,
1701 <0x0 0x03d9e000 0x0 0x2000>,
1702 <0x0 0x03d61000 0x0 0x800>;
1709 iommus = <&adreno_smmu 0 0x401>;
1731 opp-supported-hw = <0x1>;
1737 opp-supported-hw = <0x1>;
1743 opp-supported-hw = <0x3>;
1749 opp-supported-hw = <0x3>;
1755 opp-supported-hw = <0x3>;
1761 opp-supported-hw = <0x3>;
1767 opp-supported-hw = <0x3>;
1774 reg = <0x0 0x03d6a000 0x0 0x35000>,
1775 <0x0 0x03de0000 0x0 0x10000>,
1776 <0x0 0x0b290000 0x0 0x10000>;
1801 iommus = <&adreno_smmu 5 0x400>;
1824 reg = <0x0 0x03d90000 0x0 0xa000>;
1838 reg = <0x0 0x03da0000 0x0 0x10000>;
1866 reg = <0x0 0x088e3000 0x0 0x154>;
1867 #phy-cells = <0>;
1879 reg = <0x0 0x088e8000 0x0 0x3000>;
1902 #size-cells = <0>;
1904 port@0 {
1905 reg = <0>;
1931 reg = <0x0 0x0a6f8800 0x0 0x400>;
1979 reg = <0x0 0x0a600000 0x0 0xcd00>;
1981 iommus = <&apps_smmu 0x20 0x0>;
1987 snps,hird-threshold = /bits/ 8 <0x0>;
2001 #size-cells = <0>;
2003 port@0 {
2004 reg = <0>;
2023 reg = <0x0 0x0ae00000 0x0 0x1000>;
2045 iommus = <&apps_smmu 0x2000 0x402>;
2055 reg = <0x0 0x0ae01000 0x0 0x8f000>,
2056 <0x0 0x0aeb0000 0x0 0x2008>;
2061 interrupts = <0>;
2085 #size-cells = <0>;
2087 port@0 {
2088 reg = <0>;
2135 reg = <0x0 0xae90000 0x0 0x200>,
2136 <0x0 0xae90200 0x0 0x200>,
2137 <0x0 0xae90400 0x0 0xc00>,
2138 <0x0 0xae91000 0x0 0x400>,
2139 <0x0 0xae91400 0x0 0x400>;
2161 #sound-dai-cells = <0>;
2170 #size-cells = <0>;
2172 port@0 {
2173 reg = <0>;
2217 reg = <0x0 0x0ae94000 0x0 0x400>;
2240 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2249 #size-cells = <0>;
2255 #size-cells = <0>;
2257 port@0 {
2258 reg = <0>;
2293 reg = <0x0 0x0ae95000 0x0 0x200>,
2294 <0x0 0x0ae95200 0x0 0x280>,
2295 <0x0 0x0ae95500 0x0 0x400>;
2305 #phy-cells = <0>;
2313 reg = <0x0 0x0ae96000 0x0 0x400>;
2336 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2345 #size-cells = <0>;
2351 #size-cells = <0>;
2353 port@0 {
2354 reg = <0>;
2370 reg = <0x0 0x0ae97000 0x0 0x200>,
2371 <0x0 0x0ae97200 0x0 0x280>,
2372 <0x0 0x0ae97500 0x0 0x400>;
2382 #phy-cells = <0>;
2390 reg = <0x0 0x0af00000 0x0 0x20000>;
2395 <&mdss_dsi0_phy 0>,
2397 <&mdss_dsi1_phy 0>,
2401 <0>, /* dp1 */
2402 <0>,
2403 <0>, /* dp2 */
2404 <0>,
2405 <0>, /* dp3 */
2406 <0>;
2415 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
2416 qcom,pdc-ranges = <0 480 94>,
2427 reg = <0x0 0x0c300000 0x0 0x400>;
2433 #clock-cells = <0>;
2438 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */
2439 <0x0 0x0c222000 0x0 0x1000>; /* SROT */
2449 reg = <0x0 0x0c3f0000 0x0 0x400>;
2455 reg = <0x0 0x0c400000 0x0 0x3000>,
2456 <0x0 0x0c500000 0x0 0x400000>,
2457 <0x0 0x0c440000 0x0 0x80000>;
2460 qcom,ee = <0>;
2461 qcom,channel = <0>;
2468 reg = <0x0 0x0c42d000 0x0 0x4000>,
2469 <0x0 0x0c4c0000 0x0 0x10000>;
2478 #size-cells = <0>;
2484 reg = <0x0 0x0ed18000 0x0 0x1000>;
2495 reg = <0x0 0x0f100000 0x0 0x300000>;
2501 gpio-ranges = <&tlmm 0 0 156>;
2891 reg = <0x0 0x15000000 0x0 0x100000>;
2999 redistributor-stride = <0x0 0x20000>;
3000 reg = <0x0 0x17200000 0x0 0x10000>,
3001 <0x0 0x17260000 0x0 0x100000>;
3009 reg = <0x0 0x17240000 0x0 0x20000>;
3018 reg = <0x0 0x17a00000 0x0 0x10000>,
3019 <0x0 0x17a10000 0x0 0x10000>,
3020 <0x0 0x17a20000 0x0 0x10000>;
3021 reg-names = "drv-0", "drv-1", "drv-2";
3025 qcom,tcs-offset = <0xd00>;
3028 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3091 reg = <0x0 0x17d91000 0x0 0x1000>;
3096 interrupt-names = "dcvsh-irq-0";
3103 reg = <0x0 0x19100000 0x0 0xa2080>;
3114 reg = <0x0 0x19200000 0x0 0x80000>,
3115 <0x0 0x19300000 0x0 0x80000>,
3116 <0x0 0x19a00000 0x0 0x80000>,
3117 <0x0 0x19c00000 0x0 0x80000>,
3118 <0x0 0x19af0000 0x0 0x80000>,
3119 <0x0 0x19cf0000 0x0 0x80000>;
3131 reg = <0x0 0x221c8000 0x0 0x1000>;
3137 reg = <0x119 0x2>;
3144 reg = <0x0 0x320c0000 0x0 0x10>;
3151 reg = <0x0 0x3c40000 0x0 0x10>;
3168 thermal-sensors = <&tsens0 0>;
3179 hysteresis = <0>;
3504 hysteresis = <0>;
3522 hysteresis = <0>;
3540 hysteresis = <0>;
3558 hysteresis = <0>;
3576 hysteresis = <0>;