Lines Matching +full:0 +full:x00074000
30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 clocks = <&kryocc 0>;
69 reg = <0x0 0x1>;
73 clocks = <&kryocc 0>;
83 reg = <0x0 0x100>;
102 reg = <0x0 0x101>;
138 cpu_sleep_0: cpu-sleep-0 {
141 arm,psci-suspend-param = <0x00000004>;
157 opp-supported-hw = <0xf>;
163 opp-supported-hw = <0xf>;
169 opp-supported-hw = <0xf>;
175 opp-supported-hw = <0xf>;
181 opp-supported-hw = <0xf>;
187 opp-supported-hw = <0xf>;
193 opp-supported-hw = <0xf>;
199 opp-supported-hw = <0xf>;
205 opp-supported-hw = <0xf>;
211 opp-supported-hw = <0xf>;
217 opp-supported-hw = <0xf>;
223 opp-supported-hw = <0xf>;
229 opp-supported-hw = <0xd>;
235 opp-supported-hw = <0x2>;
241 opp-supported-hw = <0xd>;
247 opp-supported-hw = <0x9>;
253 opp-supported-hw = <0x04>;
259 opp-supported-hw = <0x9>;
273 opp-supported-hw = <0xf>;
279 opp-supported-hw = <0xf>;
285 opp-supported-hw = <0xf>;
291 opp-supported-hw = <0xf>;
297 opp-supported-hw = <0xf>;
303 opp-supported-hw = <0xf>;
309 opp-supported-hw = <0xf>;
315 opp-supported-hw = <0xf>;
321 opp-supported-hw = <0xf>;
327 opp-supported-hw = <0xf>;
333 opp-supported-hw = <0xf>;
339 opp-supported-hw = <0xf>;
345 opp-supported-hw = <0xf>;
351 opp-supported-hw = <0xf>;
357 opp-supported-hw = <0xf>;
363 opp-supported-hw = <0xf>;
369 opp-supported-hw = <0xf>;
375 opp-supported-hw = <0xf>;
381 opp-supported-hw = <0xf>;
387 opp-supported-hw = <0xf>;
393 opp-supported-hw = <0xe>;
399 opp-supported-hw = <0x1>;
405 opp-supported-hw = <0x4>;
411 opp-supported-hw = <0x1>;
417 opp-supported-hw = <0x1>;
423 opp-supported-hw = <0x1>;
429 opp-supported-hw = <0x1>;
438 qcom,dload-mode = <&tcsr_2 0x13000>;
445 reg = <0x0 0x80000000 0x0 0x0>;
473 mboxes = <&apcs_glb 0>;
529 reg = <0x0 0x85800000 0x0 0x600000>;
534 reg = <0x0 0x85e00000 0x0 0x200000>;
539 reg = <0x0 0x86000000 0x0 0x200000>;
544 reg = <0x0 0x86200000 0x0 0x2600000>;
551 size = <0x0 0x200000>;
552 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
560 reg = <0x0 0x88800000 0x0 0x6200000>;
565 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
570 reg = <0x0 0x90500000 0x0 0xa00000>;
576 reg = <0x0 0x90f00000 0x0 0x100000>;
581 reg = <0x0 0x91000000 0x0 0x500000>;
586 reg = <0x0 0x91500000 0x0 0x200000>;
591 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
592 size = <0x0 0x4000>;
611 qcom,local-pid = <0>;
635 qcom,local-pid = <0>;
659 qcom,local-pid = <0>;
675 soc: soc@0 {
678 ranges = <0 0 0 0xffffffff>;
683 reg = <0x00034000 0x488>;
686 ranges = <0x0 0x00034000 0x4000>;
701 reg = <0x1000 0x130>,
702 <0x1200 0x200>,
703 <0x1400 0x1dc>;
710 #clock-cells = <0>;
713 #phy-cells = <0>;
717 reg = <0x2000 0x130>,
718 <0x2200 0x200>,
719 <0x2400 0x1dc>;
726 #clock-cells = <0>;
729 #phy-cells = <0>;
733 reg = <0x3000 0x130>,
734 <0x3200 0x200>,
735 <0x3400 0x1dc>;
742 #clock-cells = <0>;
745 #phy-cells = <0>;
751 reg = <0x00068000 0x6000>;
756 reg = <0x00074000 0x8ff>;
761 reg = <0x24e 0x2>;
766 reg = <0x24f 0x1>;
771 reg = <0x133 0x1>;
778 reg = <0x00083000 0x1000>;
788 reg = <0x00300000 0x90000>;
797 <&ufsphy 0>,
814 reg = <0x00408000 0x5a000>;
820 reg = <0x004a9000 0x1000>, /* TM */
821 <0x004a8000 0x1000>; /* SROT */
831 reg = <0x004ad000 0x1000>, /* TM */
832 <0x004ac000 0x1000>; /* SROT */
842 reg = <0x00644000 0x24000>;
847 qcom,ee = <0>;
853 reg = <0x0067a000 0x6000>;
864 reg = <0x00500000 0x1000>;
870 reg = <0x00524000 0x1c000>;
876 reg = <0x00543000 0x6000>;
889 reg = <0x00562000 0x5000>;
895 reg = <0x00583000 0x7000>;
904 reg = <0x005a4000 0x1c000>;
912 reg = <0x005c0000 0x3000>;
918 reg = <0x00740000 0x20000>;
924 reg = <0x00760000 0x20000>;
929 reg = <0x007a0000 0x18000>;
937 reg = <0x008c0000 0x40000>;
969 reg = <0x00900000 0x1000>,
970 <0x009b0000 0x1040>,
971 <0x009b8000 0x1040>;
996 reg = <0x00901000 0x90000>;
1000 interrupts = <0>;
1013 iommus = <&mdp_smmu 0>;
1027 #size-cells = <0>;
1029 port@0 {
1030 reg = <0>;
1055 reg = <0x00994000 0x400>;
1084 #size-cells = <0>;
1088 #size-cells = <0>;
1090 port@0 {
1091 reg = <0>;
1107 reg = <0x00994400 0x100>,
1108 <0x00994500 0x300>,
1109 <0x00994800 0x188>;
1115 #phy-cells = <0>;
1125 reg = <0x00996000 0x400>;
1154 #size-cells = <0>;
1158 #size-cells = <0>;
1160 port@0 {
1161 reg = <0>;
1177 reg = <0x00996400 0x100>,
1178 <0x00996500 0x300>,
1179 <0x00996800 0x188>;
1185 #phy-cells = <0>;
1194 reg = <0x009a0000 0x50c>,
1195 <0x00070000 0x6158>,
1196 <0x009e0000 0xfff>;
1223 #size-cells = <0>;
1225 port@0 {
1226 reg = <0>;
1235 #phy-cells = <0>;
1237 reg = <0x009a0600 0x1c4>,
1238 <0x009a0a00 0x124>,
1239 <0x009a0c00 0x124>,
1240 <0x009a0e00 0x124>,
1241 <0x009a1000 0x124>,
1242 <0x009a1200 0x0c8>;
1257 #clock-cells = <0>;
1266 reg = <0x00b00000 0x3f000>;
1287 iommus = <&adreno_smmu 0>;
1302 * 624Mhz is only available on speed bins 0 and 3.
1303 * 560Mhz is only available on speed bins 0, 2 and 3.
1308 opp-supported-hw = <0x09>;
1312 opp-supported-hw = <0x0d>;
1316 opp-supported-hw = <0xff>;
1320 opp-supported-hw = <0xff>;
1324 opp-supported-hw = <0xff>;
1328 opp-supported-hw = <0xff>;
1332 opp-supported-hw = <0xff>;
1343 reg = <0x01010000 0x300000>;
1346 gpio-ranges = <&tlmm 0 0 150>;
1862 reg = <0x00290000 0x10000>;
1867 reg = <0x0400f000 0x1000>,
1868 <0x04400000 0x800000>,
1869 <0x04c00000 0x800000>,
1870 <0x05800000 0x200000>,
1871 <0x0400a000 0x002100>;
1875 qcom,ee = <0>;
1876 qcom,channel = <0>;
1878 #size-cells = <0>;
1883 bus@0 {
1888 ranges = <0x0 0x0 0xffffffff>;
1894 bus-range = <0x00 0xff>;
1897 reg = <0x00600000 0x2000>,
1898 <0x0c000000 0xf1d>,
1899 <0x0c000f20 0xa8>,
1900 <0x0c100000 0x100000>;
1908 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1909 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1930 interrupt-map-mask = <0 0 0 0x7>;
1931 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1932 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1933 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1934 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1937 pinctrl-0 = <&pcie0_state_on>;
1940 linux,pci-domain = <0>;
1954 pcie@0 {
1956 reg = <0x0 0x0 0x0 0x0 0x0>;
1957 bus-range = <0x01 0xff>;
1968 bus-range = <0x00 0xff>;
1973 reg = <0x00608000 0x2000>,
1974 <0x0d000000 0xf1d>,
1975 <0x0d000f20 0xa8>,
1976 <0x0d100000 0x100000>;
1985 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1986 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
2007 interrupt-map-mask = <0 0 0 0x7>;
2008 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2009 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2010 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2011 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2014 pinctrl-0 = <&pcie1_state_on>;
2031 pcie@0 {
2033 reg = <0x0 0x0 0x0 0x0 0x0>;
2034 bus-range = <0x01 0xff>;
2045 bus-range = <0x00 0xff>;
2048 reg = <0x00610000 0x2000>,
2049 <0x0e000000 0xf1d>,
2050 <0x0e000f20 0xa8>,
2051 <0x0e100000 0x100000>;
2060 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2061 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2082 interrupt-map-mask = <0 0 0 0x7>;
2083 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2084 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2085 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2086 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2089 pinctrl-0 = <&pcie2_state_on>;
2105 pcie@0 {
2107 reg = <0x0 0x0 0x0 0x0 0x0>;
2108 bus-range = <0x01 0xff>;
2120 reg = <0x00624000 0x2500>;
2150 <0 0>,
2151 <0 0>,
2152 <0 0>,
2155 <0 0>,
2156 <0 0>,
2157 <0 0>;
2170 reg = <0x00627000 0x1000>;
2175 resets = <&ufshc 0>;
2179 #phy-cells = <0>;
2186 reg = <0x00a34000 0x1000>,
2187 <0x00a00030 0x4>,
2188 <0x00a35000 0x1000>,
2189 <0x00a00038 0x4>,
2190 <0x00a36000 0x1000>,
2191 <0x00a00040 0x4>,
2192 <0x00a30000 0x100>,
2193 <0x00a30400 0x100>,
2194 <0x00a30800 0x100>,
2195 <0x00a30c00 0x100>,
2196 <0x00a31000 0x500>,
2197 <0x00a00020 0x10>,
2198 <0x00a10000 0x1000>,
2199 <0x00a14000 0x1000>;
2308 iommus = <&vfe_smmu 0>,
2315 #size-cells = <0>;
2322 #size-cells = <0>;
2323 reg = <0xa0c000 0x1000>;
2338 pinctrl-0 = <&cci0_default &cci1_default>;
2341 cci_i2c0: i2c-bus@0 {
2342 reg = <0>;
2345 #size-cells = <0>;
2352 #size-cells = <0>;
2358 reg = <0x00b40000 0x10000>;
2375 reg = <0x00c00000 0xff000>;
2386 iommus = <&venus_smmu 0x00>,
2387 <&venus_smmu 0x01>,
2388 <&venus_smmu 0x0a>,
2389 <&venus_smmu 0x07>,
2390 <&venus_smmu 0x0e>,
2391 <&venus_smmu 0x0f>,
2392 <&venus_smmu 0x08>,
2393 <&venus_smmu 0x09>,
2394 <&venus_smmu 0x0b>,
2395 <&venus_smmu 0x0c>,
2396 <&venus_smmu 0x0d>,
2397 <&venus_smmu 0x10>,
2398 <&venus_smmu 0x11>,
2399 <&venus_smmu 0x21>,
2400 <&venus_smmu 0x28>,
2401 <&venus_smmu 0x29>,
2402 <&venus_smmu 0x2b>,
2403 <&venus_smmu 0x2c>,
2404 <&venus_smmu 0x2d>,
2405 <&venus_smmu 0x31>;
2426 reg = <0x00d00000 0x10000>;
2442 reg = <0x00d40000 0x20000>;
2462 reg = <0x00da0000 0x10000>;
2477 reg = <0x01600000 0x20000>;
2503 reg = <0x01c00000 0x4000>;
2505 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2506 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2521 qcom,smem-states = <&slpi_smp2p_out 0>;
2548 reg = <0x2080000 0x100>,
2549 <0x2180000 0x020>;
2552 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2553 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2586 qcom,smem-states = <&mpss_smp2p_out 0>;
2589 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2617 qcom,smd-edge = <0>;
2624 reg = <0x3002000 0x1000>,
2625 <0x8280000 0x180000>;
2643 reg = <0x3020000 0x1000>;
2660 reg = <0x3021000 0x1000>;
2667 #size-cells = <0>;
2690 reg = <0x3022000 0x1000>;
2697 #size-cells = <0>;
2720 reg = <0x3023000 0x1000>;
2746 reg = <0x3025000 0x1000>;
2753 #size-cells = <0>;
2755 port@0 {
2756 reg = <0>;
2792 reg = <0x3026000 0x1000>;
2808 #size-cells = <0>;
2810 port@0 {
2811 reg = <0>;
2830 reg = <0x3027000 0x1000>;
2856 reg = <0x3028000 0x1000>;
2874 reg = <0x3810000 0x1000>;
2884 reg = <0x3840000 0x1000>;
2903 reg = <0x3910000 0x1000>;
2913 reg = <0x3940000 0x1000>;
2930 funnel@39b0000 { /* APSS Funnel 0 */
2932 reg = <0x39b0000 0x1000>;
2939 #size-cells = <0>;
2941 port@0 {
2942 reg = <0>;
2968 reg = <0x3a10000 0x1000>;
2978 reg = <0x3a40000 0x1000>;
2997 reg = <0x3b10000 0x1000>;
3007 reg = <0x3b40000 0x1000>;
3026 reg = <0x3bb0000 0x1000>;
3033 #size-cells = <0>;
3035 port@0 {
3036 reg = <0>;
3062 reg = <0x3bc0000 0x1000>;
3069 #size-cells = <0>;
3071 port@0 {
3072 reg = <0>;
3100 reg = <0x06400000 0x90000>;
3110 reg = <0x06af8800 0x400>;
3148 reg = <0x06a00000 0xcc00>;
3152 snps,hird-threshold = /bits/ 8 <0>;
3163 reg = <0x07410000 0x1000>;
3174 #clock-cells = <0>;
3175 #phy-cells = <0>;
3187 reg = <0x07411000 0x180>;
3188 #phy-cells = <0>;
3201 reg = <0x07412000 0x180>;
3202 #phy-cells = <0>;
3215 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3229 pinctrl-0 = <&sdc1_state_on>;
3239 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3253 pinctrl-0 = <&sdc2_state_on>;
3262 reg = <0x07544000 0x2b000>;
3268 qcom,ee = <0>;
3273 reg = <0x07570000 0x1000>;
3279 pinctrl-0 = <&blsp1_uart2_default>;
3288 reg = <0x07575000 0x600>;
3294 pinctrl-0 = <&blsp1_spi1_default>;
3299 #size-cells = <0>;
3305 reg = <0x07577000 0x1000>;
3311 pinctrl-0 = <&blsp1_i2c3_default>;
3316 #size-cells = <0>;
3322 reg = <0x757a000 0x1000>;
3328 pinctrl-0 = <&blsp1_i2c6_default>;
3333 #size-cells = <0>;
3339 reg = <0x07584000 0x2b000>;
3345 qcom,ee = <0>;
3350 reg = <0x075b0000 0x1000>;
3360 reg = <0x075b1000 0x1000>;
3370 reg = <0x075b5000 0x1000>;
3376 pinctrl-0 = <&blsp2_i2c1_default>;
3381 #size-cells = <0>;
3387 reg = <0x075b6000 0x1000>;
3393 pinctrl-0 = <&blsp2_i2c2_default>;
3398 #size-cells = <0>;
3404 reg = <0x075b7000 0x1000>;
3411 pinctrl-0 = <&blsp2_i2c3_default>;
3416 #size-cells = <0>;
3422 reg = <0x75b9000 0x1000>;
3428 pinctrl-0 = <&blsp2_i2c5_default>;
3432 #size-cells = <0>;
3438 reg = <0x75ba000 0x1000>;
3444 pinctrl-0 = <&blsp2_i2c6_default>;
3449 #size-cells = <0>;
3455 reg = <0x075ba000 0x600>;
3461 pinctrl-0 = <&blsp2_spi6_default>;
3466 #size-cells = <0>;
3472 reg = <0x076f8800 0x400>;
3505 reg = <0x07600000 0xcc00>;
3518 reg = <0x09184000 0x32000>;
3528 reg = <0x091c0000 0x2c000>;
3533 #size-cells = <0>;
3540 reg = <0x09300000 0x80000>;
3542 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3543 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3555 qcom,smem-states = <&adsp_smp2p_out 0>;
3585 #size-cells = <0>;
3598 #size-cells = <0>;
3612 #size-cells = <0>;
3623 #sound-dai-cells = <0>;
3634 #size-cells = <0>;
3689 reg = <0x09820000 0x1000>;
3692 #clock-cells = <0>;
3700 reg = <0x09840000 0x1000>;
3704 frame-number = <0>;
3707 reg = <0x09850000 0x1000>,
3708 <0x09860000 0x1000>;
3714 reg = <0x09870000 0x1000>;
3721 reg = <0x09880000 0x1000>;
3728 reg = <0x09890000 0x1000>;
3735 reg = <0x098a0000 0x1000>;
3742 reg = <0x098b0000 0x1000>;
3749 reg = <0x098c0000 0x1000>;
3756 reg = <0x09a10000 0x1000>;
3761 reg = <0x09a11000 0x10000>;
3763 #clock-cells = <0>;
3772 redistributor-stride = <0x0 0x40000>;
3773 reg = <0x09bc0000 0x10000>,
3774 <0x09c00000 0x100000>;