Lines Matching +full:i2c +full:- +full:qup +full:- +full:v1
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
11 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
12 #include <dt-bindings/interconnect/qcom,ipq9574.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 ref_48mhz_clk: ref-48mhz-clk {
24 compatible = "fixed-factor-clock";
26 #clock-cells = <0>;
29 sleep_clk: sleep-clk {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
34 xo_board_clk: xo-board-clk {
35 compatible = "fixed-factor-clock";
37 #clock-cells = <0>;
40 xo_clk: xo-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a73";
54 enable-method = "psci";
55 next-level-cache = <&l2_0>;
57 clock-names = "cpu";
58 operating-points-v2 = <&cpu_opp_table>;
59 cpu-supply = <&ipq9574_s1>;
60 #cooling-cells = <2>;
65 compatible = "arm,cortex-a73";
67 enable-method = "psci";
68 next-level-cache = <&l2_0>;
70 clock-names = "cpu";
71 operating-points-v2 = <&cpu_opp_table>;
72 cpu-supply = <&ipq9574_s1>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a73";
80 enable-method = "psci";
81 next-level-cache = <&l2_0>;
83 clock-names = "cpu";
84 operating-points-v2 = <&cpu_opp_table>;
85 cpu-supply = <&ipq9574_s1>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a73";
93 enable-method = "psci";
94 next-level-cache = <&l2_0>;
96 clock-names = "cpu";
97 operating-points-v2 = <&cpu_opp_table>;
98 cpu-supply = <&ipq9574_s1>;
99 #cooling-cells = <2>;
102 l2_0: l2-cache {
104 cache-level = <2>;
105 cache-unified;
111 compatible = "qcom,scm-ipq9574", "qcom,scm";
112 qcom,dload-mode = <&tcsr 0x6100>;
122 cpu_opp_table: opp-table-cpu {
123 compatible = "operating-points-v2-kryo-cpu";
124 opp-shared;
125 nvmem-cells = <&cpu_speed_bin>;
127 opp-936000000 {
128 opp-hz = /bits/ 64 <936000000>;
129 opp-microvolt = <725000>;
130 opp-supported-hw = <0xf>;
131 clock-latency-ns = <200000>;
134 opp-1104000000 {
135 opp-hz = /bits/ 64 <1104000000>;
136 opp-microvolt = <787500>;
137 opp-supported-hw = <0xf>;
138 clock-latency-ns = <200000>;
141 opp-1200000000 {
142 opp-hz = /bits/ 64 <1200000000>;
143 opp-microvolt = <862500>;
144 opp-supported-hw = <0xf>;
145 clock-latency-ns = <200000>;
148 opp-1416000000 {
149 opp-hz = /bits/ 64 <1416000000>;
150 opp-microvolt = <862500>;
151 opp-supported-hw = <0x7>;
152 clock-latency-ns = <200000>;
155 opp-1488000000 {
156 opp-hz = /bits/ 64 <1488000000>;
157 opp-microvolt = <925000>;
158 opp-supported-hw = <0x7>;
159 clock-latency-ns = <200000>;
162 opp-1800000000 {
163 opp-hz = /bits/ 64 <1800000000>;
164 opp-microvolt = <987500>;
165 opp-supported-hw = <0x5>;
166 clock-latency-ns = <200000>;
169 opp-2208000000 {
170 opp-hz = /bits/ 64 <2208000000>;
171 opp-microvolt = <1062500>;
172 opp-supported-hw = <0x1>;
173 clock-latency-ns = <200000>;
178 compatible = "arm,cortex-a73-pmu";
183 compatible = "arm,psci-1.0";
188 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
190 glink-edge {
191 compatible = "qcom,glink-rpm";
193 qcom,rpm-msg-ram = <&rpm_msg_ram>;
196 rpm_requests: rpm-requests {
197 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
198 qcom,glink-channels = "rpm_requests";
203 reserved-memory {
204 #address-cells = <2>;
205 #size-cells = <2>;
210 no-map;
215 no-map;
220 no-map;
227 no-map;
232 compatible = "simple-bus";
233 #address-cells = <1>;
234 #size-cells = <1>;
238 compatible = "qcom,rpm-msg-ram";
243 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
249 clock-names = "aux", "cfg_ahb", "pipe";
251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
252 assigned-clock-rates = <20000000>;
256 reset-names = "phy", "common";
258 #clock-cells = <0>;
259 clock-output-names = "gcc_pcie0_pipe_clk_src";
261 #phy-cells = <0>;
266 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
272 clock-names = "aux", "cfg_ahb", "pipe";
274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
275 assigned-clock-rates = <20000000>;
279 reset-names = "phy", "common";
281 #clock-cells = <0>;
282 clock-output-names = "gcc_pcie2_pipe_clk_src";
284 #phy-cells = <0>;
289 compatible = "qcom,ipq9574-trng", "qcom,trng";
292 clock-names = "core";
296 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
298 #address-cells = <1>;
299 #size-cells = <0>;
301 clock-names = "gcc_mdio_ahb_clk";
306 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
312 clock-names = "aux", "cfg_ahb", "pipe";
314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
315 assigned-clock-rates = <20000000>;
319 reset-names = "phy", "common";
321 #clock-cells = <0>;
322 clock-output-names = "gcc_pcie3_pipe_clk_src";
324 #phy-cells = <0>;
329 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
335 clock-names = "aux", "cfg_ahb", "pipe";
337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
338 assigned-clock-rates = <20000000>;
342 reset-names = "phy", "common";
344 #clock-cells = <0>;
345 clock-output-names = "gcc_pcie1_pipe_clk_src";
347 #phy-cells = <0>;
351 cmn_pll: clock-controller@9b000 {
352 compatible = "qcom,ipq9574-cmn-pll";
357 clock-names = "ref", "ahb", "sys";
358 #clock-cells = <1>;
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
360 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
364 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
366 #address-cells = <1>;
367 #size-cells = <1>;
369 cpu_speed_bin: cpu-speed-bin@15 {
375 cryptobam: dma-controller@704000 {
376 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
379 #dma-cells = <1>;
381 qcom,num-ees = <4>;
382 num-channels = <16>;
383 qcom,controlled-remotely;
387 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
392 clock-names = "iface", "bus", "core";
394 dma-names = "rx", "tx";
397 tsens: thermal-sensor@4a9000 {
398 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
402 interrupt-names = "combined";
404 #thermal-sensor-cells = <1>;
408 compatible = "qcom,ipq9574-tlmm";
411 gpio-controller;
412 #gpio-cells = <2>;
413 gpio-ranges = <&tlmm 0 0 65>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
417 uart2_pins: uart2-state {
420 drive-strength = <8>;
421 bias-disable;
425 gcc: clock-controller@1800000 {
426 compatible = "qcom,ipq9574-gcc";
436 #clock-cells = <1>;
437 #reset-cells = <1>;
438 #interconnect-cells = <1>;
442 compatible = "qcom,tcsr-mutex";
444 #hwlock-cells = <1>;
448 compatible = "qcom,tcsr-ipq9574", "syscon";
453 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
457 reg-names = "hc", "cqhci", "ice";
461 interrupt-names = "hc_irq", "pwr_irq";
467 clock-names = "iface", "core", "xo", "ice";
468 non-removable;
469 supports-cqe;
473 blsp_dma: dma-controller@7884000 {
474 compatible = "qcom,bam-v1.7.0";
478 clock-names = "bam_clk";
479 #dma-cells = <1>;
484 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
489 clock-names = "core", "iface";
494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
499 clock-names = "core", "iface";
504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
509 clock-names = "core", "iface";
514 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
519 clock-names = "core", "iface";
524 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
529 clock-names = "core", "iface";
534 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
539 clock-names = "core", "iface";
544 compatible = "qcom,spi-qup-v2.2.1";
546 #address-cells = <1>;
547 #size-cells = <0>;
551 clock-names = "core", "iface";
553 dma-names = "tx", "rx";
557 blsp1_i2c1: i2c@78b6000 {
558 compatible = "qcom,i2c-qup-v2.2.1";
560 #address-cells = <1>;
561 #size-cells = <0>;
565 clock-names = "core", "iface";
566 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
567 assigned-clock-rates = <50000000>;
569 dma-names = "tx", "rx";
574 compatible = "qcom,spi-qup-v2.2.1";
576 #address-cells = <1>;
577 #size-cells = <0>;
581 clock-names = "core", "iface";
583 dma-names = "tx", "rx";
587 blsp1_i2c2: i2c@78b7000 {
588 compatible = "qcom,i2c-qup-v2.2.1";
590 #address-cells = <1>;
591 #size-cells = <0>;
595 clock-names = "core", "iface";
596 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
597 assigned-clock-rates = <50000000>;
599 dma-names = "tx", "rx";
604 compatible = "qcom,spi-qup-v2.2.1";
606 #address-cells = <1>;
607 #size-cells = <0>;
611 clock-names = "core", "iface";
613 dma-names = "tx", "rx";
617 blsp1_i2c3: i2c@78b8000 {
618 compatible = "qcom,i2c-qup-v2.2.1";
620 #address-cells = <1>;
621 #size-cells = <0>;
625 clock-names = "core", "iface";
626 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
627 assigned-clock-rates = <50000000>;
629 dma-names = "tx", "rx";
634 compatible = "qcom,spi-qup-v2.2.1";
636 #address-cells = <1>;
637 #size-cells = <0>;
639 spi-max-frequency = <50000000>;
642 clock-names = "core", "iface";
644 dma-names = "tx", "rx";
648 blsp1_i2c4: i2c@78b9000 {
649 compatible = "qcom,i2c-qup-v2.2.1";
651 #address-cells = <1>;
652 #size-cells = <0>;
656 clock-names = "core", "iface";
657 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
658 assigned-clock-rates = <50000000>;
660 dma-names = "tx", "rx";
665 compatible = "qcom,spi-qup-v2.2.1";
667 #address-cells = <1>;
668 #size-cells = <0>;
672 clock-names = "core", "iface";
674 dma-names = "tx", "rx";
678 qpic_bam: dma-controller@7984000 {
679 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
683 clock-names = "bam_clk";
684 #dma-cells = <1>;
690 compatible = "qcom,ipq9574-snand";
692 #address-cells = <1>;
693 #size-cells = <0>;
697 clock-names = "core", "aon", "iom";
701 dma-names = "tx", "rx", "cmd";
706 compatible = "qcom,ipq9574-qusb2-phy";
708 #phy-cells = <0>;
712 clock-names = "cfg_ahb",
720 compatible = "qcom,ipq9574-qmp-usb3-phy";
722 #phy-cells = <0>;
728 clock-names = "aux",
735 reset-names = "phy",
738 #clock-cells = <0>;
739 clock-output-names = "usb0_pipe_clk";
745 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
747 #address-cells = <1>;
748 #size-cells = <1>;
757 clock-names = "cfg_noc",
763 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
765 assigned-clock-rates = <200000000>,
768 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
769 interrupt-names = "pwr_event";
778 clock-names = "ref";
781 phy-names = "usb2-phy", "usb3-phy";
782 tx-fifo-resize;
783 snps,is-utmi-l1-suspend;
784 snps,hird-threshold = /bits/ 8 <0x0>;
790 intc: interrupt-controller@b000000 {
791 compatible = "qcom,msm-qgic2";
796 #address-cells = <1>;
797 #size-cells = <1>;
798 interrupt-controller;
799 #interrupt-cells = <3>;
804 compatible = "arm,gic-v2m-frame";
806 msi-controller;
810 compatible = "arm,gic-v2m-frame";
812 msi-controller;
816 compatible = "arm,gic-v2m-frame";
818 msi-controller;
823 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
827 timeout-sec = <30>;
831 compatible = "qcom,ipq9574-apcs-apps-global",
832 "qcom,ipq6018-apcs-apps-global";
834 #clock-cells = <1>;
836 clock-names = "pll", "xo", "gpll0";
837 #mbox-cells = <1>;
841 compatible = "qcom,ipq9574-a73pll";
843 #clock-cells = <0>;
845 clock-names = "xo";
849 compatible = "arm,armv7-timer-mem";
851 #address-cells = <1>;
852 #size-cells = <1>;
858 frame-number = <0>;
865 frame-number = <1>;
872 frame-number = <2>;
879 frame-number = <3>;
886 frame-number = <4>;
893 frame-number = <5>;
900 frame-number = <6>;
907 compatible = "qcom,pcie-ipq9574";
914 reg-names = "dbi",
921 linux,pci-domain = <1>;
922 bus-range = <0x00 0xff>;
923 num-lanes = <1>;
924 #address-cells = <3>;
925 #size-cells = <2>;
938 interrupt-names = "msi0",
947 #interrupt-cells = <1>;
948 interrupt-map-mask = <0 0 0 0x7>;
949 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
960 clock-names = "axi_m",
975 reset-names = "pipe",
985 phy-names = "pciephy";
988 interconnect-names = "pcie-mem", "cpu-pcie";
993 compatible = "qcom,pcie-ipq9574";
1000 reg-names = "dbi",
1007 linux,pci-domain = <3>;
1008 bus-range = <0x00 0xff>;
1009 num-lanes = <2>;
1010 #address-cells = <3>;
1011 #size-cells = <2>;
1024 interrupt-names = "msi0",
1033 #interrupt-cells = <1>;
1034 interrupt-map-mask = <0 0 0 0x7>;
1035 interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
1046 clock-names = "axi_m",
1061 reset-names = "pipe",
1071 phy-names = "pciephy";
1074 interconnect-names = "pcie-mem", "cpu-pcie";
1079 compatible = "qcom,pcie-ipq9574";
1086 reg-names = "dbi",
1093 linux,pci-domain = <2>;
1094 bus-range = <0x00 0xff>;
1095 num-lanes = <2>;
1096 #address-cells = <3>;
1097 #size-cells = <2>;
1110 interrupt-names = "msi0",
1119 #interrupt-cells = <1>;
1120 interrupt-map-mask = <0 0 0 0x7>;
1121 interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
1132 clock-names = "axi_m",
1147 reset-names = "pipe",
1157 phy-names = "pciephy";
1160 interconnect-names = "pcie-mem", "cpu-pcie";
1165 compatible = "qcom,pcie-ipq9574";
1172 reg-names = "dbi",
1179 linux,pci-domain = <0>;
1180 bus-range = <0x00 0xff>;
1181 num-lanes = <1>;
1182 #address-cells = <3>;
1183 #size-cells = <2>;
1195 interrupt-names = "msi0",
1204 #interrupt-cells = <1>;
1205 interrupt-map-mask = <0 0 0 0x7>;
1206 interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
1217 clock-names = "axi_m",
1232 reset-names = "pipe",
1242 phy-names = "pciephy";
1245 interconnect-names = "pcie-mem", "cpu-pcie";
1249 nsscc: clock-controller@39b00000 {
1250 compatible = "qcom,ipq9574-nsscc";
1263 clock-names = "xo",
1274 #clock-cells = <1>;
1275 #reset-cells = <1>;
1276 #interconnect-cells = <1>;
1280 thermal-zones {
1281 nss-top-thermal {
1282 thermal-sensors = <&tsens 3>;
1285 nss-top-critical {
1293 ubi-0-thermal {
1294 thermal-sensors = <&tsens 4>;
1297 ubi_0-critical {
1305 ubi-1-thermal {
1306 thermal-sensors = <&tsens 5>;
1309 ubi_1-critical {
1317 ubi-2-thermal {
1318 thermal-sensors = <&tsens 6>;
1321 ubi_2-critical {
1329 ubi-3-thermal {
1330 thermal-sensors = <&tsens 7>;
1333 ubi_3-critical {
1341 cpuss0-thermal {
1342 thermal-sensors = <&tsens 8>;
1345 cpu-critical {
1353 cpuss1-thermal {
1354 thermal-sensors = <&tsens 9>;
1357 cpu-critical {
1365 cpu0-thermal {
1366 thermal-sensors = <&tsens 10>;
1369 cpu0_crit: cpu-critical {
1375 cpu0_alert: cpu-passive {
1382 cooling-maps {
1385 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1393 cpu1-thermal {
1394 thermal-sensors = <&tsens 11>;
1397 cpu1_crit: cpu-critical {
1403 cpu1_alert: cpu-passive {
1410 cooling-maps {
1413 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1421 cpu2-thermal {
1422 thermal-sensors = <&tsens 12>;
1425 cpu2_crit: cpu-critical {
1431 cpu2_alert: cpu-passive {
1438 cooling-maps {
1441 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1449 cpu3-thermal {
1450 thermal-sensors = <&tsens 13>;
1453 cpu3_crit: cpu-critical {
1459 cpu3_alert: cpu-passive {
1466 cooling-maps {
1469 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1477 wcss-phyb-thermal {
1478 thermal-sensors = <&tsens 14>;
1481 wcss_phyb-critical {
1489 top-glue-thermal {
1490 thermal-sensors = <&tsens 15>;
1493 top_glue-critical {
1503 compatible = "arm,armv8-timer";