Lines Matching +full:0 +full:x004a9000
26 #clock-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
112 qcom,dload-mode = <&tcsr 0x6100>;
119 reg = <0x0 0x40000000 0x0 0x0>;
130 opp-supported-hw = <0xf>;
137 opp-supported-hw = <0xf>;
144 opp-supported-hw = <0xf>;
151 opp-supported-hw = <0x7>;
158 opp-supported-hw = <0x7>;
165 opp-supported-hw = <0x5>;
172 opp-supported-hw = <0x1>;
194 mboxes = <&apcs_glb 0>;
209 reg = <0x0 0x4a100000 0x0 0x400000>;
214 reg = <0x0 0x4a500000 0x0 0x100000>;
219 reg = <0x0 0x4a600000 0x0 0x400000>;
225 reg = <0x0 0x4aa00000 0x0 0x100000>;
231 soc: soc@0 {
235 ranges = <0 0 0 0xffffffff>;
239 reg = <0x00060000 0x6000>;
244 reg = <0x00084000 0x1000>;
258 #clock-cells = <0>;
261 #phy-cells = <0>;
267 reg = <0x0008c000 0x2000>;
281 #clock-cells = <0>;
284 #phy-cells = <0>;
290 reg = <0x000e3000 0x1000>;
297 reg = <0x00090000 0x64>;
299 #size-cells = <0>;
307 reg = <0x000f4000 0x2000>;
321 #clock-cells = <0>;
324 #phy-cells = <0>;
330 reg = <0x000fc000 0x1000>;
344 #clock-cells = <0>;
347 #phy-cells = <0>;
353 reg = <0x0009b000 0x800>;
365 reg = <0x000a4000 0x5a1>;
370 reg = <0x15 0x2>;
377 reg = <0x00704000 0x20000>;
388 reg = <0x0073a000 0x6000>;
399 reg = <0x004a9000 0x1000>,
400 <0x004a8000 0x1000>;
409 reg = <0x01000000 0x300000>;
413 gpio-ranges = <&tlmm 0 0 65>;
427 reg = <0x01800000 0x80000>;
430 <0>,
435 <0>;
443 reg = <0x01905000 0x20000>;
449 reg = <0x01937000 0x21000>;
454 reg = <0x07804000 0x1000>,
455 <0x07805000 0x1000>,
456 <0x07808000 0x2000>;
475 reg = <0x07884000 0x2b000>;
480 qcom,ee = <0>;
485 reg = <0x078af000 0x200>;
495 reg = <0x078b0000 0x200>;
505 reg = <0x078b1000 0x200>;
515 reg = <0x078b2000 0x200>;
525 reg = <0x078b3000 0x200>;
535 reg = <0x078b4000 0x200>;
545 reg = <0x078b5000 0x600>;
547 #size-cells = <0>;
559 reg = <0x078b6000 0x600>;
561 #size-cells = <0>;
575 reg = <0x078b6000 0x600>;
577 #size-cells = <0>;
589 reg = <0x078b7000 0x600>;
591 #size-cells = <0>;
605 reg = <0x078b7000 0x600>;
607 #size-cells = <0>;
619 reg = <0x078b8000 0x600>;
621 #size-cells = <0>;
635 reg = <0x078b8000 0x600>;
637 #size-cells = <0>;
650 reg = <0x078b9000 0x600>;
652 #size-cells = <0>;
666 reg = <0x078b9000 0x600>;
668 #size-cells = <0>;
680 reg = <0x07984000 0x1c000>;
685 qcom,ee = <0>;
691 reg = <0x079b0000 0x10000>;
693 #size-cells = <0>;
698 dmas = <&qpic_bam 0>,
707 reg = <0x0007b000 0x180>;
708 #phy-cells = <0>;
721 reg = <0x0007d000 0xa00>;
722 #phy-cells = <0>;
738 #clock-cells = <0>;
746 reg = <0x08af8800 0x400>;
776 reg = <0x8a00000 0xcd00>;
784 snps,hird-threshold = /bits/ 8 <0x0>;
792 reg = <0x0b000000 0x1000>, /* GICD */
793 <0x0b002000 0x2000>, /* GICC */
794 <0x0b001000 0x1000>, /* GICH */
795 <0x0b004000 0x2000>; /* GICV */
801 ranges = <0 0x0b00c000 0x3000>;
803 v2m0: v2m@0 {
805 reg = <0x00000000 0xffd>;
811 reg = <0x00001000 0xffd>;
817 reg = <0x00002000 0xffd>;
824 reg = <0x0b017000 0x1000>;
833 reg = <0x0b111000 0x1000>;
842 reg = <0x0b116000 0x40>;
843 #clock-cells = <0>;
850 reg = <0x0b120000 0x1000>;
856 reg = <0x0b121000 0x1000>,
857 <0x0b122000 0x1000>;
858 frame-number = <0>;
864 reg = <0x0b123000 0x1000>;
871 reg = <0x0b124000 0x1000>;
878 reg = <0x0b125000 0x1000>;
885 reg = <0x0b126000 0x1000>;
892 reg = <0x0b127000 0x1000>;
899 reg = <0x0b128000 0x1000>;
908 reg = <0x10000000 0xf1d>,
909 <0x10000f20 0xa8>,
910 <0x10001000 0x1000>,
911 <0x000f8000 0x4000>,
912 <0x10100000 0x1000>,
913 <0x000fe000 0x1000>;
922 bus-range = <0x00 0xff>;
927 ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
928 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
948 interrupt-map-mask = <0 0 0 0x7>;
949 interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
950 <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
951 <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
952 <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
994 reg = <0x18000000 0xf1d>,
995 <0x18000f20 0xa8>,
996 <0x18001000 0x1000>,
997 <0x000f0000 0x4000>,
998 <0x18100000 0x1000>,
999 <0x000f6000 0x1000>;
1008 bus-range = <0x00 0xff>;
1013 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
1014 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
1034 interrupt-map-mask = <0 0 0 0x7>;
1035 interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
1036 <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
1037 <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
1038 <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
1080 reg = <0x20000000 0xf1d>,
1081 <0x20000f20 0xa8>,
1082 <0x20001000 0x1000>,
1083 <0x00088000 0x4000>,
1084 <0x20100000 0x1000>,
1085 <0x0008e000 0x1000>;
1094 bus-range = <0x00 0xff>;
1099 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
1100 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
1120 interrupt-map-mask = <0 0 0 0x7>;
1121 interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
1122 <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
1123 <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
1124 <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
1166 reg = <0x28000000 0xf1d>,
1167 <0x28000f20 0xa8>,
1168 <0x28001000 0x1000>,
1169 <0x00080000 0x4000>,
1170 <0x28100000 0x1000>,
1171 <0x00086000 0x1000>;
1179 linux,pci-domain = <0>;
1180 bus-range = <0x00 0xff>;
1185 ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
1186 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
1205 interrupt-map-mask = <0 0 0 0x7>;
1206 interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
1207 <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
1208 <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
1209 <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
1251 reg = <0x39b00000 0x80000>;
1256 <0>,
1257 <0>,
1258 <0>,
1259 <0>,
1260 <0>,
1261 <0>,
1293 ubi-0-thermal {