Lines Matching +full:tegra234 +full:- +full:ccplex +full:- +full:cluster
1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
14 compatible = "nvidia,tegra234";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
32 compatible = "simple-bus";
34 #address-cells = <2>;
35 #size-cells = <2>;
39 compatible = "nvidia,tegra234-misc";
46 compatible = "nvidia,tegra234-timer";
68 compatible = "nvidia,tegra234-gpio";
69 reg-names = "security", "gpio";
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 #gpio-cells = <2>;
123 gpio-controller;
124 gpio-ranges = <&pinmux 0 0 164>;
128 compatible = "nvidia,tegra234-pinmux";
132 gpcdma: dma-controller@2600000 {
133 compatible = "nvidia,tegra234-gpcdma",
134 "nvidia,tegra186-gpcdma";
137 reset-names = "gpcdma";
170 #dma-cells = <1>;
172 dma-channel-mask = <0xfffffffe>;
173 dma-coherent;
177 compatible = "nvidia,tegra234-aconnect",
178 "nvidia,tegra210-aconnect";
181 clock-names = "ape", "apb2ape";
182 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
185 #address-cells = <2>;
186 #size-cells = <2>;
190 compatible = "nvidia,tegra234-ahub";
193 clock-names = "ahub";
194 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
195 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
196 assigned-clock-rates = <81600000>;
199 #address-cells = <2>;
200 #size-cells = <2>;
204 compatible = "nvidia,tegra234-i2s",
205 "nvidia,tegra210-i2s";
209 clock-names = "i2s", "sync_input";
210 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
211 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
212 assigned-clock-rates = <1536000>;
213 sound-name-prefix = "I2S1";
217 #address-cells = <1>;
218 #size-cells = <0>;
224 remote-endpoint = <&xbar_i2s1>;
232 dai-format = "i2s";
240 compatible = "nvidia,tegra234-i2s",
241 "nvidia,tegra210-i2s";
245 clock-names = "i2s", "sync_input";
246 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
247 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
248 assigned-clock-rates = <1536000>;
249 sound-name-prefix = "I2S2";
253 #address-cells = <1>;
254 #size-cells = <0>;
260 remote-endpoint = <&xbar_i2s2>;
268 dai-format = "i2s";
276 compatible = "nvidia,tegra234-i2s",
277 "nvidia,tegra210-i2s";
281 clock-names = "i2s", "sync_input";
282 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
283 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
284 assigned-clock-rates = <1536000>;
285 sound-name-prefix = "I2S3";
289 #address-cells = <1>;
290 #size-cells = <0>;
296 remote-endpoint = <&xbar_i2s3>;
304 dai-format = "i2s";
312 compatible = "nvidia,tegra234-i2s",
313 "nvidia,tegra210-i2s";
317 clock-names = "i2s", "sync_input";
318 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
319 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
320 assigned-clock-rates = <1536000>;
321 sound-name-prefix = "I2S4";
325 #address-cells = <1>;
326 #size-cells = <0>;
332 remote-endpoint = <&xbar_i2s4>;
340 dai-format = "i2s";
348 compatible = "nvidia,tegra234-i2s",
349 "nvidia,tegra210-i2s";
353 clock-names = "i2s", "sync_input";
354 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
355 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
356 assigned-clock-rates = <1536000>;
357 sound-name-prefix = "I2S5";
361 #address-cells = <1>;
362 #size-cells = <0>;
368 remote-endpoint = <&xbar_i2s5>;
376 dai-format = "i2s";
384 compatible = "nvidia,tegra234-i2s",
385 "nvidia,tegra210-i2s";
389 clock-names = "i2s", "sync_input";
390 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
391 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
392 assigned-clock-rates = <1536000>;
393 sound-name-prefix = "I2S6";
397 #address-cells = <1>;
398 #size-cells = <0>;
404 remote-endpoint = <&xbar_i2s6>;
412 dai-format = "i2s";
420 compatible = "nvidia,tegra234-sfc",
421 "nvidia,tegra210-sfc";
423 sound-name-prefix = "SFC1";
426 #address-cells = <1>;
427 #size-cells = <0>;
433 remote-endpoint = <&xbar_sfc1_in>;
441 remote-endpoint = <&xbar_sfc1_out>;
448 compatible = "nvidia,tegra234-sfc",
449 "nvidia,tegra210-sfc";
451 sound-name-prefix = "SFC2";
454 #address-cells = <1>;
455 #size-cells = <0>;
461 remote-endpoint = <&xbar_sfc2_in>;
469 remote-endpoint = <&xbar_sfc2_out>;
476 compatible = "nvidia,tegra234-sfc",
477 "nvidia,tegra210-sfc";
479 sound-name-prefix = "SFC3";
482 #address-cells = <1>;
483 #size-cells = <0>;
489 remote-endpoint = <&xbar_sfc3_in>;
497 remote-endpoint = <&xbar_sfc3_out>;
504 compatible = "nvidia,tegra234-sfc",
505 "nvidia,tegra210-sfc";
507 sound-name-prefix = "SFC4";
510 #address-cells = <1>;
511 #size-cells = <0>;
517 remote-endpoint = <&xbar_sfc4_in>;
525 remote-endpoint = <&xbar_sfc4_out>;
532 compatible = "nvidia,tegra234-amx",
533 "nvidia,tegra194-amx";
535 sound-name-prefix = "AMX1";
538 #address-cells = <1>;
539 #size-cells = <0>;
545 remote-endpoint = <&xbar_amx1_in1>;
553 remote-endpoint = <&xbar_amx1_in2>;
561 remote-endpoint = <&xbar_amx1_in3>;
569 remote-endpoint = <&xbar_amx1_in4>;
577 remote-endpoint = <&xbar_amx1_out>;
584 compatible = "nvidia,tegra234-amx",
585 "nvidia,tegra194-amx";
587 sound-name-prefix = "AMX2";
590 #address-cells = <1>;
591 #size-cells = <0>;
597 remote-endpoint = <&xbar_amx2_in1>;
605 remote-endpoint = <&xbar_amx2_in2>;
613 remote-endpoint = <&xbar_amx2_in3>;
621 remote-endpoint = <&xbar_amx2_in4>;
629 remote-endpoint = <&xbar_amx2_out>;
636 compatible = "nvidia,tegra234-amx",
637 "nvidia,tegra194-amx";
639 sound-name-prefix = "AMX3";
642 #address-cells = <1>;
643 #size-cells = <0>;
649 remote-endpoint = <&xbar_amx3_in1>;
657 remote-endpoint = <&xbar_amx3_in2>;
665 remote-endpoint = <&xbar_amx3_in3>;
673 remote-endpoint = <&xbar_amx3_in4>;
681 remote-endpoint = <&xbar_amx3_out>;
688 compatible = "nvidia,tegra234-amx",
689 "nvidia,tegra194-amx";
691 sound-name-prefix = "AMX4";
694 #address-cells = <1>;
695 #size-cells = <0>;
701 remote-endpoint = <&xbar_amx4_in1>;
709 remote-endpoint = <&xbar_amx4_in2>;
717 remote-endpoint = <&xbar_amx4_in3>;
725 remote-endpoint = <&xbar_amx4_in4>;
733 remote-endpoint = <&xbar_amx4_out>;
740 compatible = "nvidia,tegra234-adx",
741 "nvidia,tegra210-adx";
743 sound-name-prefix = "ADX1";
746 #address-cells = <1>;
747 #size-cells = <0>;
753 remote-endpoint = <&xbar_adx1_in>;
761 remote-endpoint = <&xbar_adx1_out1>;
769 remote-endpoint = <&xbar_adx1_out2>;
777 remote-endpoint = <&xbar_adx1_out3>;
785 remote-endpoint = <&xbar_adx1_out4>;
792 compatible = "nvidia,tegra234-adx",
793 "nvidia,tegra210-adx";
795 sound-name-prefix = "ADX2";
798 #address-cells = <1>;
799 #size-cells = <0>;
805 remote-endpoint = <&xbar_adx2_in>;
813 remote-endpoint = <&xbar_adx2_out1>;
821 remote-endpoint = <&xbar_adx2_out2>;
829 remote-endpoint = <&xbar_adx2_out3>;
837 remote-endpoint = <&xbar_adx2_out4>;
844 compatible = "nvidia,tegra234-adx",
845 "nvidia,tegra210-adx";
847 sound-name-prefix = "ADX3";
850 #address-cells = <1>;
851 #size-cells = <0>;
857 remote-endpoint = <&xbar_adx3_in>;
865 remote-endpoint = <&xbar_adx3_out1>;
873 remote-endpoint = <&xbar_adx3_out2>;
881 remote-endpoint = <&xbar_adx3_out3>;
889 remote-endpoint = <&xbar_adx3_out4>;
896 compatible = "nvidia,tegra234-adx",
897 "nvidia,tegra210-adx";
899 sound-name-prefix = "ADX4";
902 #address-cells = <1>;
903 #size-cells = <0>;
909 remote-endpoint = <&xbar_adx4_in>;
917 remote-endpoint = <&xbar_adx4_out1>;
925 remote-endpoint = <&xbar_adx4_out2>;
933 remote-endpoint = <&xbar_adx4_out3>;
941 remote-endpoint = <&xbar_adx4_out4>;
949 compatible = "nvidia,tegra234-dmic",
950 "nvidia,tegra210-dmic";
953 clock-names = "dmic";
954 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
955 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
956 assigned-clock-rates = <3072000>;
957 sound-name-prefix = "DMIC1";
961 #address-cells = <1>;
962 #size-cells = <0>;
968 remote-endpoint = <&xbar_dmic1>;
983 compatible = "nvidia,tegra234-dmic",
984 "nvidia,tegra210-dmic";
987 clock-names = "dmic";
988 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
989 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
990 assigned-clock-rates = <3072000>;
991 sound-name-prefix = "DMIC2";
995 #address-cells = <1>;
996 #size-cells = <0>;
1002 remote-endpoint = <&xbar_dmic2>;
1017 compatible = "nvidia,tegra234-dmic",
1018 "nvidia,tegra210-dmic";
1021 clock-names = "dmic";
1022 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
1023 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1024 assigned-clock-rates = <3072000>;
1025 sound-name-prefix = "DMIC3";
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1036 remote-endpoint = <&xbar_dmic3>;
1051 compatible = "nvidia,tegra234-dmic",
1052 "nvidia,tegra210-dmic";
1055 clock-names = "dmic";
1056 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
1057 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1058 assigned-clock-rates = <3072000>;
1059 sound-name-prefix = "DMIC4";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1070 remote-endpoint = <&xbar_dmic4>;
1085 compatible = "nvidia,tegra234-dspk",
1086 "nvidia,tegra186-dspk";
1089 clock-names = "dspk";
1090 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
1091 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1092 assigned-clock-rates = <12288000>;
1093 sound-name-prefix = "DSPK1";
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1104 remote-endpoint = <&xbar_dspk1>;
1119 compatible = "nvidia,tegra234-dspk",
1120 "nvidia,tegra186-dspk";
1123 clock-names = "dspk";
1124 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
1125 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
1126 assigned-clock-rates = <12288000>;
1127 sound-name-prefix = "DSPK2";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1138 remote-endpoint = <&xbar_dspk2>;
1152 tegra_ope1: processing-engine@2908000 {
1153 compatible = "nvidia,tegra234-ope",
1154 "nvidia,tegra210-ope";
1156 sound-name-prefix = "OPE1";
1158 #address-cells = <2>;
1159 #size-cells = <2>;
1163 compatible = "nvidia,tegra234-peq",
1164 "nvidia,tegra210-peq";
1168 dynamic-range-compressor@2908200 {
1169 compatible = "nvidia,tegra234-mbdrc",
1170 "nvidia,tegra210-mbdrc";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1182 remote-endpoint =
1191 remote-endpoint =
1199 compatible = "nvidia,tegra234-mvc",
1200 "nvidia,tegra210-mvc";
1202 sound-name-prefix = "MVC1";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1212 remote-endpoint = <&xbar_mvc1_in>;
1220 remote-endpoint = <&xbar_mvc1_out>;
1227 compatible = "nvidia,tegra234-mvc",
1228 "nvidia,tegra210-mvc";
1230 sound-name-prefix = "MVC2";
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1240 remote-endpoint = <&xbar_mvc2_in>;
1248 remote-endpoint = <&xbar_mvc2_out>;
1255 compatible = "nvidia,tegra234-amixer",
1256 "nvidia,tegra210-amixer";
1258 sound-name-prefix = "MIXER1";
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1268 remote-endpoint = <&xbar_mix_in1>;
1276 remote-endpoint = <&xbar_mix_in2>;
1284 remote-endpoint = <&xbar_mix_in3>;
1292 remote-endpoint = <&xbar_mix_in4>;
1300 remote-endpoint = <&xbar_mix_in5>;
1308 remote-endpoint = <&xbar_mix_in6>;
1316 remote-endpoint = <&xbar_mix_in7>;
1324 remote-endpoint = <&xbar_mix_in8>;
1332 remote-endpoint = <&xbar_mix_in9>;
1340 remote-endpoint = <&xbar_mix_in10>;
1348 remote-endpoint = <&xbar_mix_out1>;
1356 remote-endpoint = <&xbar_mix_out2>;
1364 remote-endpoint = <&xbar_mix_out3>;
1372 remote-endpoint = <&xbar_mix_out4>;
1380 remote-endpoint = <&xbar_mix_out5>;
1387 compatible = "nvidia,tegra234-admaif",
1388 "nvidia,tegra186-admaif";
1410 dma-names = "rx1", "tx1",
1432 interconnect-names = "dma-mem", "write";
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1443 remote-endpoint = <&xbar_admaif0>;
1451 remote-endpoint = <&xbar_admaif1>;
1459 remote-endpoint = <&xbar_admaif2>;
1467 remote-endpoint = <&xbar_admaif3>;
1475 remote-endpoint = <&xbar_admaif4>;
1483 remote-endpoint = <&xbar_admaif5>;
1491 remote-endpoint = <&xbar_admaif6>;
1499 remote-endpoint = <&xbar_admaif7>;
1507 remote-endpoint = <&xbar_admaif8>;
1515 remote-endpoint = <&xbar_admaif9>;
1523 remote-endpoint = <&xbar_admaif10>;
1531 remote-endpoint = <&xbar_admaif11>;
1539 remote-endpoint = <&xbar_admaif12>;
1547 remote-endpoint = <&xbar_admaif13>;
1555 remote-endpoint = <&xbar_admaif14>;
1563 remote-endpoint = <&xbar_admaif15>;
1571 remote-endpoint = <&xbar_admaif16>;
1579 remote-endpoint = <&xbar_admaif17>;
1587 remote-endpoint = <&xbar_admaif18>;
1595 remote-endpoint = <&xbar_admaif19>;
1602 compatible = "nvidia,tegra234-asrc",
1603 "nvidia,tegra186-asrc";
1605 sound-name-prefix = "ASRC1";
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1615 remote-endpoint =
1624 remote-endpoint =
1633 remote-endpoint =
1642 remote-endpoint =
1651 remote-endpoint =
1660 remote-endpoint =
1669 remote-endpoint =
1678 remote-endpoint =
1687 remote-endpoint =
1696 remote-endpoint =
1705 remote-endpoint =
1714 remote-endpoint =
1723 remote-endpoint =
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1738 remote-endpoint = <&admaif0>;
1746 remote-endpoint = <&admaif1>;
1754 remote-endpoint = <&admaif2>;
1762 remote-endpoint = <&admaif3>;
1770 remote-endpoint = <&admaif4>;
1778 remote-endpoint = <&admaif5>;
1786 remote-endpoint = <&admaif6>;
1794 remote-endpoint = <&admaif7>;
1802 remote-endpoint = <&admaif8>;
1810 remote-endpoint = <&admaif9>;
1818 remote-endpoint = <&admaif10>;
1826 remote-endpoint = <&admaif11>;
1834 remote-endpoint = <&admaif12>;
1842 remote-endpoint = <&admaif13>;
1850 remote-endpoint = <&admaif14>;
1858 remote-endpoint = <&admaif15>;
1866 remote-endpoint = <&admaif16>;
1874 remote-endpoint = <&admaif17>;
1882 remote-endpoint = <&admaif18>;
1890 remote-endpoint = <&admaif19>;
1898 remote-endpoint = <&i2s1_cif>;
1906 remote-endpoint = <&i2s2_cif>;
1914 remote-endpoint = <&i2s3_cif>;
1922 remote-endpoint = <&i2s4_cif>;
1930 remote-endpoint = <&i2s5_cif>;
1938 remote-endpoint = <&i2s6_cif>;
1946 remote-endpoint = <&dmic1_cif>;
1954 remote-endpoint = <&dmic2_cif>;
1962 remote-endpoint = <&dmic3_cif>;
1970 remote-endpoint = <&dmic4_cif>;
1978 remote-endpoint = <&dspk1_cif>;
1986 remote-endpoint = <&dspk2_cif>;
1994 remote-endpoint = <&sfc1_cif_in>;
2002 remote-endpoint = <&sfc1_cif_out>;
2010 remote-endpoint = <&sfc2_cif_in>;
2018 remote-endpoint = <&sfc2_cif_out>;
2026 remote-endpoint = <&sfc3_cif_in>;
2034 remote-endpoint = <&sfc3_cif_out>;
2042 remote-endpoint = <&sfc4_cif_in>;
2050 remote-endpoint = <&sfc4_cif_out>;
2058 remote-endpoint = <&mvc1_cif_in>;
2066 remote-endpoint = <&mvc1_cif_out>;
2074 remote-endpoint = <&mvc2_cif_in>;
2082 remote-endpoint = <&mvc2_cif_out>;
2090 remote-endpoint = <&amx1_in1>;
2098 remote-endpoint = <&amx1_in2>;
2106 remote-endpoint = <&amx1_in3>;
2114 remote-endpoint = <&amx1_in4>;
2122 remote-endpoint = <&amx1_out>;
2130 remote-endpoint = <&amx2_in1>;
2138 remote-endpoint = <&amx2_in2>;
2146 remote-endpoint = <&amx2_in3>;
2154 remote-endpoint = <&amx2_in4>;
2162 remote-endpoint = <&amx2_out>;
2170 remote-endpoint = <&amx3_in1>;
2178 remote-endpoint = <&amx3_in2>;
2186 remote-endpoint = <&amx3_in3>;
2194 remote-endpoint = <&amx3_in4>;
2202 remote-endpoint = <&amx3_out>;
2210 remote-endpoint = <&amx4_in1>;
2218 remote-endpoint = <&amx4_in2>;
2226 remote-endpoint = <&amx4_in3>;
2234 remote-endpoint = <&amx4_in4>;
2242 remote-endpoint = <&amx4_out>;
2250 remote-endpoint = <&adx1_in>;
2258 remote-endpoint = <&adx1_out1>;
2266 remote-endpoint = <&adx1_out2>;
2274 remote-endpoint = <&adx1_out3>;
2282 remote-endpoint = <&adx1_out4>;
2290 remote-endpoint = <&adx2_in>;
2298 remote-endpoint = <&adx2_out1>;
2306 remote-endpoint = <&adx2_out2>;
2314 remote-endpoint = <&adx2_out3>;
2322 remote-endpoint = <&adx2_out4>;
2330 remote-endpoint = <&adx3_in>;
2338 remote-endpoint = <&adx3_out1>;
2346 remote-endpoint = <&adx3_out2>;
2354 remote-endpoint = <&adx3_out3>;
2362 remote-endpoint = <&adx3_out4>;
2370 remote-endpoint = <&adx4_in>;
2378 remote-endpoint = <&adx4_out1>;
2386 remote-endpoint = <&adx4_out2>;
2394 remote-endpoint = <&adx4_out3>;
2402 remote-endpoint = <&adx4_out4>;
2410 remote-endpoint = <&mix_in1>;
2418 remote-endpoint = <&mix_in2>;
2426 remote-endpoint = <&mix_in3>;
2434 remote-endpoint = <&mix_in4>;
2442 remote-endpoint = <&mix_in5>;
2450 remote-endpoint = <&mix_in6>;
2458 remote-endpoint = <&mix_in7>;
2466 remote-endpoint = <&mix_in8>;
2474 remote-endpoint = <&mix_in9>;
2482 remote-endpoint = <&mix_in10>;
2490 remote-endpoint = <&mix_out1>;
2498 remote-endpoint = <&mix_out2>;
2506 remote-endpoint = <&mix_out3>;
2514 remote-endpoint = <&mix_out4>;
2522 remote-endpoint = <&mix_out5>;
2530 remote-endpoint = <&asrc_in1_ep>;
2538 remote-endpoint = <&asrc_out1_ep>;
2546 remote-endpoint = <&asrc_in2_ep>;
2554 remote-endpoint = <&asrc_out2_ep>;
2562 remote-endpoint = <&asrc_in3_ep>;
2570 remote-endpoint = <&asrc_out3_ep>;
2578 remote-endpoint = <&asrc_in4_ep>;
2586 remote-endpoint = <&asrc_out4_ep>;
2594 remote-endpoint = <&asrc_in5_ep>;
2602 remote-endpoint = <&asrc_out5_ep>;
2610 remote-endpoint = <&asrc_in6_ep>;
2618 remote-endpoint = <&asrc_out6_ep>;
2626 remote-endpoint = <&asrc_in7_ep>;
2634 remote-endpoint = <&ope1_cif_in_ep>;
2642 remote-endpoint = <&ope1_cif_out_ep>;
2648 adma: dma-controller@2930000 {
2649 compatible = "nvidia,tegra234-adma",
2650 "nvidia,tegra186-adma";
2652 interrupt-parent = <&agic>;
2685 #dma-cells = <1>;
2687 clock-names = "d_audio";
2691 agic: interrupt-controller@2a40000 {
2692 compatible = "nvidia,tegra234-agic",
2693 "nvidia,tegra210-agic";
2694 #interrupt-cells = <3>;
2695 interrupt-controller;
2702 clock-names = "clk";
2707 mc: memory-controller@2c00000 {
2708 compatible = "nvidia,tegra234-mc";
2709 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
2727 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
2731 #interconnect-cells = <1>;
2734 #address-cells = <2>;
2735 #size-cells = <2>;
2755 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
2757 emc: external-memory-controller@2c60000 {
2758 compatible = "nvidia,tegra234-emc";
2763 clock-names = "emc";
2766 #interconnect-cells = <0>;
2773 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2779 dma-names = "rx", "tx";
2784 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2790 dma-names = "rx", "tx";
2795 compatible = "nvidia,tegra194-i2c";
2799 #address-cells = <1>;
2800 #size-cells = <0>;
2801 clock-frequency = <400000>;
2804 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
2805 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2806 clock-names = "div-clk", "parent";
2808 reset-names = "i2c";
2810 dma-names = "rx", "tx";
2814 compatible = "nvidia,tegra194-i2c";
2817 #address-cells = <1>;
2818 #size-cells = <0>;
2820 clock-frequency = <400000>;
2823 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
2824 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2825 clock-names = "div-clk", "parent";
2827 reset-names = "i2c";
2829 dma-names = "rx", "tx";
2833 compatible = "nvidia,tegra194-i2c";
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2839 clock-frequency = <100000>;
2842 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
2843 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2844 clock-names = "div-clk", "parent";
2846 reset-names = "i2c";
2848 dma-names = "rx", "tx";
2852 compatible = "nvidia,tegra194-i2c";
2855 #address-cells = <1>;
2856 #size-cells = <0>;
2858 clock-frequency = <100000>;
2861 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
2862 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2863 clock-names = "div-clk", "parent";
2865 reset-names = "i2c";
2867 dma-names = "rx", "tx";
2871 compatible = "nvidia,tegra194-i2c";
2874 #address-cells = <1>;
2875 #size-cells = <0>;
2877 clock-frequency = <100000>;
2880 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
2881 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2882 clock-names = "div-clk", "parent";
2884 reset-names = "i2c";
2886 dma-names = "rx", "tx";
2890 compatible = "arm,sbsa-uart";
2897 compatible = "nvidia,tegra194-i2c";
2900 #address-cells = <1>;
2901 #size-cells = <0>;
2903 clock-frequency = <100000>;
2906 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
2907 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2908 clock-names = "div-clk", "parent";
2910 reset-names = "i2c";
2912 dma-names = "rx", "tx";
2916 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2919 #address-cells = <1>;
2920 #size-cells = <0>;
2922 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
2923 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2924 clock-names = "spi";
2927 reset-names = "spi";
2929 dma-names = "rx", "tx";
2930 dma-coherent;
2935 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
2938 #address-cells = <1>;
2939 #size-cells = <0>;
2941 clock-names = "spi";
2943 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
2944 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
2946 reset-names = "spi";
2948 dma-names = "rx", "tx";
2949 dma-coherent;
2954 compatible = "nvidia,tegra234-qspi";
2957 #address-cells = <1>;
2958 #size-cells = <0>;
2961 clock-names = "qspi", "qspi_out";
2964 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
2966 assigned-clock-rates = <199999999 99999999>;
2967 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
2972 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2976 reset-names = "pwm";
2978 #pwm-cells = <2>;
2982 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2986 reset-names = "pwm";
2988 #pwm-cells = <2>;
2992 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2996 reset-names = "pwm";
2998 #pwm-cells = <2>;
3002 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3006 reset-names = "pwm";
3008 #pwm-cells = <2>;
3012 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3016 reset-names = "pwm";
3018 #pwm-cells = <2>;
3022 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3026 reset-names = "pwm";
3028 #pwm-cells = <2>;
3032 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3036 reset-names = "pwm";
3038 #pwm-cells = <2>;
3042 compatible = "nvidia,tegra234-qspi";
3045 #address-cells = <1>;
3046 #size-cells = <0>;
3049 clock-names = "qspi", "qspi_out";
3052 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
3054 assigned-clock-rates = <199999999 99999999>;
3055 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
3060 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3065 clock-names = "sdhci", "tmclk";
3066 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
3068 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
3071 reset-names = "sdhci";
3074 interconnect-names = "dma-mem", "write";
3076 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
3077 pinctrl-0 = <&sdmmc1_3v3>;
3078 pinctrl-1 = <&sdmmc1_1v8>;
3079 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
3080 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
3081 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
3082 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
3083 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
3084 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
3085 nvidia,default-tap = <14>;
3086 nvidia,default-trim = <0x8>;
3087 sd-uhs-sdr25;
3088 sd-uhs-sdr50;
3089 sd-uhs-ddr50;
3090 sd-uhs-sdr104;
3095 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
3100 clock-names = "sdhci", "tmclk";
3101 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
3103 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
3105 reset-names = "sdhci";
3108 interconnect-names = "dma-mem", "write";
3110 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
3111 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
3112 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
3113 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
3114 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
3115 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
3116 nvidia,default-tap = <0x8>;
3117 nvidia,default-trim = <0x14>;
3118 nvidia,dqs-trim = <40>;
3119 supports-cqe;
3124 compatible = "nvidia,tegra234-hda";
3129 clock-names = "hda", "hda2codec_2x";
3132 reset-names = "hda", "hda2codec_2x";
3133 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
3136 interconnect-names = "dma-mem", "write";
3142 compatible = "nvidia,tegra234-xusb-padctl";
3145 reg-names = "padctl", "ao";
3149 reset-names = "padctl";
3156 clock-names = "trk";
3159 usb2-0 {
3162 #phy-cells = <0>;
3165 usb2-1 {
3168 #phy-cells = <0>;
3171 usb2-2 {
3174 #phy-cells = <0>;
3177 usb2-3 {
3180 #phy-cells = <0>;
3187 usb3-0 {
3190 #phy-cells = <0>;
3193 usb3-1 {
3196 #phy-cells = <0>;
3199 usb3-2 {
3202 #phy-cells = <0>;
3205 usb3-3 {
3208 #phy-cells = <0>;
3215 usb2-0 {
3219 usb2-1 {
3223 usb2-2 {
3227 usb2-3 {
3231 usb3-0 {
3235 usb3-1 {
3239 usb3-2 {
3243 usb3-3 {
3250 compatible = "nvidia,tegra234-xudc";
3253 reg-names = "base", "fpci";
3259 clock-names = "dev", "ss", "ss_src", "fs_src";
3262 interconnect-names = "dma-mem", "write";
3264 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
3266 power-domain-names = "dev", "ss";
3267 nvidia,xusb-padctl = <&xusb_padctl>;
3268 dma-coherent;
3273 compatible = "nvidia,tegra234-xusb";
3277 reg-names = "hcd", "fpci", "bar2";
3291 clock-names = "xusb_host", "xusb_falcon_src",
3297 interconnect-names = "dma-mem", "write";
3300 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
3302 power-domain-names = "xusb_host", "xusb_ss";
3304 nvidia,xusb-padctl = <&xusb_padctl>;
3305 dma-coherent;
3310 compatible = "nvidia,tegra234-efuse";
3313 clock-names = "fuse";
3316 hte_lic: hardware-timestamp@3aa0000 {
3317 compatible = "nvidia,tegra234-gte-lic";
3320 nvidia,int-threshold = <1>;
3321 #timestamp-cells = <1>;
3325 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3336 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
3339 #mbox-cells = <2>;
3343 compatible = "nvidia,tegra234-p2u";
3345 reg-names = "ctl";
3347 #phy-cells = <0>;
3351 compatible = "nvidia,tegra234-p2u";
3353 reg-names = "ctl";
3355 #phy-cells = <0>;
3359 compatible = "nvidia,tegra234-p2u";
3361 reg-names = "ctl";
3363 #phy-cells = <0>;
3367 compatible = "nvidia,tegra234-p2u";
3369 reg-names = "ctl";
3371 #phy-cells = <0>;
3375 compatible = "nvidia,tegra234-p2u";
3377 reg-names = "ctl";
3379 #phy-cells = <0>;
3383 compatible = "nvidia,tegra234-p2u";
3385 reg-names = "ctl";
3387 #phy-cells = <0>;
3391 compatible = "nvidia,tegra234-p2u";
3393 reg-names = "ctl";
3395 #phy-cells = <0>;
3399 compatible = "nvidia,tegra234-p2u";
3401 reg-names = "ctl";
3403 #phy-cells = <0>;
3407 compatible = "nvidia,tegra234-p2u";
3409 reg-names = "ctl";
3411 #phy-cells = <0>;
3415 compatible = "nvidia,tegra234-p2u";
3417 reg-names = "ctl";
3419 #phy-cells = <0>;
3423 compatible = "nvidia,tegra234-p2u";
3425 reg-names = "ctl";
3427 #phy-cells = <0>;
3431 compatible = "nvidia,tegra234-p2u";
3433 reg-names = "ctl";
3435 #phy-cells = <0>;
3439 compatible = "nvidia,tegra234-p2u";
3441 reg-names = "ctl";
3443 #phy-cells = <0>;
3447 compatible = "nvidia,tegra234-p2u";
3449 reg-names = "ctl";
3451 #phy-cells = <0>;
3455 compatible = "nvidia,tegra234-p2u";
3457 reg-names = "ctl";
3459 #phy-cells = <0>;
3463 compatible = "nvidia,tegra234-p2u";
3465 reg-names = "ctl";
3467 #phy-cells = <0>;
3471 compatible = "nvidia,tegra234-p2u";
3473 reg-names = "ctl";
3475 #phy-cells = <0>;
3479 compatible = "nvidia,tegra234-p2u";
3481 reg-names = "ctl";
3483 #phy-cells = <0>;
3487 compatible = "nvidia,tegra234-p2u";
3489 reg-names = "ctl";
3491 #phy-cells = <0>;
3495 compatible = "nvidia,tegra234-p2u";
3497 reg-names = "ctl";
3499 #phy-cells = <0>;
3503 compatible = "nvidia,tegra234-p2u";
3505 reg-names = "ctl";
3507 #phy-cells = <0>;
3511 compatible = "nvidia,tegra234-p2u";
3513 reg-names = "ctl";
3515 #phy-cells = <0>;
3519 compatible = "nvidia,tegra234-p2u";
3521 reg-names = "ctl";
3523 #phy-cells = <0>;
3527 compatible = "nvidia,tegra234-p2u";
3529 reg-names = "ctl";
3531 #phy-cells = <0>;
3535 compatible = "nvidia,tegra234-mgbe";
3539 reg-names = "hypervisor", "mac", "xpcs";
3541 interrupt-names = "common";
3554 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3555 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3556 "rx-pcs", "tx-pcs";
3559 reset-names = "mac", "pcs";
3562 interconnect-names = "dma-mem", "write";
3564 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
3567 snps,axi-config = <&mgbe0_axi_setup>;
3569 mgbe0_axi_setup: stmmac-axi-config {
3577 compatible = "nvidia,tegra234-mgbe";
3581 reg-names = "hypervisor", "mac", "xpcs";
3583 interrupt-names = "common";
3596 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3597 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3598 "rx-pcs", "tx-pcs";
3601 reset-names = "mac", "pcs";
3604 interconnect-names = "dma-mem", "write";
3606 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
3609 snps,axi-config = <&mgbe1_axi_setup>;
3611 mgbe1_axi_setup: stmmac-axi-config {
3619 compatible = "nvidia,tegra234-mgbe";
3623 reg-names = "hypervisor", "mac", "xpcs";
3625 interrupt-names = "common";
3638 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3639 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3640 "rx-pcs", "tx-pcs";
3643 reset-names = "mac", "pcs";
3646 interconnect-names = "dma-mem", "write";
3648 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3651 snps,axi-config = <&mgbe2_axi_setup>;
3653 mgbe2_axi_setup: stmmac-axi-config {
3661 compatible = "nvidia,tegra234-mgbe";
3665 reg-names = "hypervisor", "mac", "xpcs";
3667 interrupt-names = "common";
3680 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
3681 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
3682 "rx-pcs", "tx-pcs";
3685 reset-names = "mac", "pcs";
3688 interconnect-names = "dma-mem", "write";
3690 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
3695 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
3828 stream-match-mask = <0x7f80>;
3829 #global-interrupts = <2>;
3830 #iommu-cells = <1>;
3832 nvidia,memory-controller = <&mc>;
3836 sce-fabric@b600000 {
3837 compatible = "nvidia,tegra234-sce-fabric";
3843 rce-fabric@be00000 {
3844 compatible = "nvidia,tegra234-rce-fabric";
3851 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3859 * we only have 4 shared interrupts for the CCPLEX.
3861 interrupt-names = "shared1", "shared2", "shared3", "shared4";
3862 #mbox-cells = <2>;
3865 hte_aon: hardware-timestamp@c1e0000 {
3866 compatible = "nvidia,tegra234-gte-aon";
3869 nvidia,int-threshold = <1>;
3870 nvidia,gpio-controller = <&gpio_aon>;
3871 #timestamp-cells = <1>;
3875 compatible = "nvidia,tegra194-i2c";
3878 #address-cells = <1>;
3879 #size-cells = <0>;
3881 clock-frequency = <100000>;
3884 clock-names = "div-clk", "parent";
3885 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
3886 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3888 reset-names = "i2c";
3890 dma-names = "rx", "tx";
3894 compatible = "nvidia,tegra194-i2c";
3897 #address-cells = <1>;
3898 #size-cells = <0>;
3900 clock-frequency = <400000>;
3903 clock-names = "div-clk", "parent";
3904 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
3905 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3907 reset-names = "i2c";
3909 dma-names = "rx", "tx";
3913 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
3916 #address-cells = <1>;
3917 #size-cells = <0>;
3919 clock-names = "spi";
3921 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
3922 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
3924 reset-names = "spi";
3926 dma-names = "rx", "tx";
3927 dma-coherent;
3932 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
3934 interrupt-parent = <&pmc>;
3937 clock-names = "rtc";
3942 compatible = "nvidia,tegra234-gpio-aon";
3943 reg-names = "security", "gpio";
3950 #interrupt-cells = <2>;
3951 interrupt-controller;
3952 #gpio-cells = <2>;
3953 gpio-controller;
3954 gpio-ranges = <&pinmux_aon 0 0 32>;
3958 compatible = "nvidia,tegra234-pinmux-aon";
3963 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
3967 reset-names = "pwm";
3969 #pwm-cells = <2>;
3973 compatible = "nvidia,tegra234-pmc";
3979 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
3981 #interrupt-cells = <2>;
3982 interrupt-controller;
3984 sdmmc1_1v8: sdmmc1-1v8 {
3985 pins = "sdmmc1-hv";
3986 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3989 sdmmc1_3v3: sdmmc1-3v3 {
3990 pins = "sdmmc1-hv";
3991 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
3994 sdmmc3_1v8: sdmmc3-1v8 {
3995 pins = "sdmmc3-hv";
3996 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
3999 sdmmc3_3v3: sdmmc3-3v3 {
4000 pins = "sdmmc3-hv";
4001 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
4005 aon-fabric@c600000 {
4006 compatible = "nvidia,tegra234-aon-fabric";
4012 bpmp-fabric@d600000 {
4013 compatible = "nvidia,tegra234-bpmp-fabric";
4019 dce-fabric@de00000 {
4020 compatible = "nvidia,tegra234-dce-fabric";
4026 ccplex@e000000 {
4027 compatible = "nvidia,tegra234-ccplex-cluster";
4033 gic: interrupt-controller@f400000 {
4034 compatible = "arm,gic-v3";
4037 interrupt-parent = <&gic>;
4040 #redistributor-regions = <1>;
4041 #interrupt-cells = <3>;
4042 interrupt-controller;
4044 #address-cells = <0>;
4048 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4179 stream-match-mask = <0x7f80>;
4180 #global-interrupts = <1>;
4181 #iommu-cells = <1>;
4183 nvidia,memory-controller = <&mc>;
4188 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
4321 stream-match-mask = <0x7f80>;
4322 #global-interrupts = <2>;
4323 #iommu-cells = <1>;
4325 nvidia,memory-controller = <&mc>;
4329 cbb-fabric@13a00000 {
4330 compatible = "nvidia,tegra234-cbb-fabric";
4337 compatible = "nvidia,tegra234-host1x";
4341 reg-names = "common", "hypervisor", "vm";
4351 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
4354 clock-names = "host1x";
4356 #address-cells = <2>;
4357 #size-cells = <2>;
4361 interconnect-names = "dma-mem";
4363 dma-coherent;
4366 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
4384 compatible = "nvidia,tegra234-vic";
4388 clock-names = "vic";
4390 reset-names = "vic";
4392 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
4395 interconnect-names = "dma-mem", "write";
4397 dma-coherent;
4401 compatible = "nvidia,tegra234-nvdec";
4406 clock-names = "nvdec", "fuse", "tsec_pka";
4408 reset-names = "nvdec";
4409 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
4412 interconnect-names = "dma-mem", "write";
4414 dma-coherent;
4416 nvidia,memory-controller = <&mc>;
4422 nvidia,bl-manifest-offset = <0>;
4423 nvidia,bl-data-offset = <0>;
4424 nvidia,bl-code-offset = <0>;
4425 nvidia,os-manifest-offset = <0>;
4426 nvidia,os-data-offset = <0>;
4427 nvidia,os-code-offset = <0>;
4437 compatible = "nvidia,tegra234-se-aes";
4441 dma-coherent;
4445 compatible = "nvidia,tegra234-se-hash";
4449 dma-coherent;
4454 compatible = "nvidia,tegra234-pcie";
4455 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
4461 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4463 #address-cells = <3>;
4464 #size-cells = <2>;
4466 num-lanes = <4>;
4467 num-viewport = <8>;
4468 linux,pci-domain = <8>;
4471 clock-names = "core";
4475 reset-names = "apb", "core";
4479 interrupt-names = "intr", "msi";
4481 #interrupt-cells = <1>;
4482 interrupt-map-mask = <0 0 0 0>;
4483 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
4487 nvidia,aspm-cmrt-us = <60>;
4488 nvidia,aspm-pwr-on-t-us = <20>;
4489 nvidia,aspm-l0s-entrance-latency-us = <3>;
4491 bus-range = <0x0 0xff>;
4494 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4499 interconnect-names = "dma-mem", "write";
4500 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
4501 iommu-map-mask = <0x0>;
4502 dma-coherent;
4508 compatible = "nvidia,tegra234-pcie";
4509 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
4515 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4517 #address-cells = <3>;
4518 #size-cells = <2>;
4520 num-lanes = <4>;
4521 num-viewport = <8>;
4522 linux,pci-domain = <9>;
4525 clock-names = "core";
4529 reset-names = "apb", "core";
4533 interrupt-names = "intr", "msi";
4535 #interrupt-cells = <1>;
4536 interrupt-map-mask = <0 0 0 0>;
4537 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
4541 nvidia,aspm-cmrt-us = <60>;
4542 nvidia,aspm-pwr-on-t-us = <20>;
4543 nvidia,aspm-l0s-entrance-latency-us = <3>;
4545 bus-range = <0x0 0xff>;
4548 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4553 interconnect-names = "dma-mem", "write";
4554 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
4555 iommu-map-mask = <0x0>;
4556 dma-coherent;
4562 compatible = "nvidia,tegra234-pcie";
4563 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4569 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4571 #address-cells = <3>;
4572 #size-cells = <2>;
4574 num-lanes = <4>;
4575 num-viewport = <8>;
4576 linux,pci-domain = <10>;
4579 clock-names = "core";
4583 reset-names = "apb", "core";
4587 interrupt-names = "intr", "msi";
4589 #interrupt-cells = <1>;
4590 interrupt-map-mask = <0 0 0 0>;
4591 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4595 nvidia,aspm-cmrt-us = <60>;
4596 nvidia,aspm-pwr-on-t-us = <20>;
4597 nvidia,aspm-l0s-entrance-latency-us = <3>;
4599 bus-range = <0x0 0xff>;
4602 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4607 interconnect-names = "dma-mem", "write";
4608 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4609 iommu-map-mask = <0x0>;
4610 dma-coherent;
4615 pcie-ep@140e0000 {
4616 compatible = "nvidia,tegra234-pcie-ep";
4617 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
4622 reg-names = "appl", "atu_dma", "dbi", "addr_space";
4624 num-lanes = <4>;
4627 clock-names = "core";
4631 reset-names = "apb", "core";
4634 interrupt-names = "intr";
4638 nvidia,enable-ext-refclk;
4639 nvidia,aspm-cmrt-us = <60>;
4640 nvidia,aspm-pwr-on-t-us = <20>;
4641 nvidia,aspm-l0s-entrance-latency-us = <3>;
4645 interconnect-names = "dma-mem", "write";
4646 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
4647 iommu-map-mask = <0x0>;
4648 dma-coherent;
4654 compatible = "nvidia,tegra234-pcie";
4655 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4661 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4663 #address-cells = <3>;
4664 #size-cells = <2>;
4666 num-lanes = <1>;
4667 num-viewport = <8>;
4668 linux,pci-domain = <1>;
4671 clock-names = "core";
4675 reset-names = "apb", "core";
4679 interrupt-names = "intr", "msi";
4681 #interrupt-cells = <1>;
4682 interrupt-map-mask = <0 0 0 0>;
4683 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
4687 nvidia,aspm-cmrt-us = <60>;
4688 nvidia,aspm-pwr-on-t-us = <20>;
4689 nvidia,aspm-l0s-entrance-latency-us = <3>;
4691 bus-range = <0x0 0xff>;
4694 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4699 interconnect-names = "dma-mem", "write";
4700 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
4701 iommu-map-mask = <0x0>;
4702 dma-coherent;
4708 compatible = "nvidia,tegra234-pcie";
4709 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4715 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4717 #address-cells = <3>;
4718 #size-cells = <2>;
4720 num-lanes = <1>;
4721 num-viewport = <8>;
4722 linux,pci-domain = <2>;
4725 clock-names = "core";
4729 reset-names = "apb", "core";
4733 interrupt-names = "intr", "msi";
4735 #interrupt-cells = <1>;
4736 interrupt-map-mask = <0 0 0 0>;
4737 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
4741 nvidia,aspm-cmrt-us = <60>;
4742 nvidia,aspm-pwr-on-t-us = <20>;
4743 nvidia,aspm-l0s-entrance-latency-us = <3>;
4745 bus-range = <0x0 0xff>;
4748 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4753 interconnect-names = "dma-mem", "write";
4754 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
4755 iommu-map-mask = <0x0>;
4756 dma-coherent;
4762 compatible = "nvidia,tegra234-pcie";
4763 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
4769 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4771 #address-cells = <3>;
4772 #size-cells = <2>;
4774 num-lanes = <1>;
4775 num-viewport = <8>;
4776 linux,pci-domain = <3>;
4779 clock-names = "core";
4783 reset-names = "apb", "core";
4787 interrupt-names = "intr", "msi";
4789 #interrupt-cells = <1>;
4790 interrupt-map-mask = <0 0 0 0>;
4791 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4795 nvidia,aspm-cmrt-us = <60>;
4796 nvidia,aspm-pwr-on-t-us = <20>;
4797 nvidia,aspm-l0s-entrance-latency-us = <3>;
4799 bus-range = <0x0 0xff>;
4802 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4807 interconnect-names = "dma-mem", "write";
4808 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
4809 iommu-map-mask = <0x0>;
4810 dma-coherent;
4816 compatible = "nvidia,tegra234-pcie";
4817 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4823 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4825 #address-cells = <3>;
4826 #size-cells = <2>;
4828 num-lanes = <4>;
4829 num-viewport = <8>;
4830 linux,pci-domain = <4>;
4833 clock-names = "core";
4837 reset-names = "apb", "core";
4841 interrupt-names = "intr", "msi";
4843 #interrupt-cells = <1>;
4844 interrupt-map-mask = <0 0 0 0>;
4845 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4849 nvidia,aspm-cmrt-us = <60>;
4850 nvidia,aspm-pwr-on-t-us = <20>;
4851 nvidia,aspm-l0s-entrance-latency-us = <3>;
4853 bus-range = <0x0 0xff>;
4856 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4861 interconnect-names = "dma-mem", "write";
4862 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
4863 iommu-map-mask = <0x0>;
4864 dma-coherent;
4869 pcie-ep@14160000 {
4870 compatible = "nvidia,tegra234-pcie-ep";
4871 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
4876 reg-names = "appl", "atu_dma", "dbi", "addr_space";
4877 num-lanes = <4>;
4879 clock-names = "core";
4882 reset-names = "apb", "core";
4885 interrupt-names = "intr";
4887 nvidia,enable-ext-refclk;
4888 nvidia,aspm-cmrt-us = <60>;
4889 nvidia,aspm-pwr-on-t-us = <20>;
4890 nvidia,aspm-l0s-entrance-latency-us = <3>;
4894 interconnect-names = "dma-mem", "write";
4896 dma-coherent;
4901 compatible = "nvidia,tegra234-pcie";
4902 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
4908 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4910 #address-cells = <3>;
4911 #size-cells = <2>;
4913 num-lanes = <4>;
4914 num-viewport = <8>;
4915 linux,pci-domain = <0>;
4918 clock-names = "core";
4922 reset-names = "apb", "core";
4926 interrupt-names = "intr", "msi";
4928 #interrupt-cells = <1>;
4929 interrupt-map-mask = <0 0 0 0>;
4930 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4934 nvidia,aspm-cmrt-us = <60>;
4935 nvidia,aspm-pwr-on-t-us = <20>;
4936 nvidia,aspm-l0s-entrance-latency-us = <3>;
4938 bus-range = <0x0 0xff>;
4941 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
4946 interconnect-names = "dma-mem", "write";
4947 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
4948 iommu-map-mask = <0x0>;
4949 dma-coherent;
4955 compatible = "nvidia,tegra234-pcie";
4956 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
4962 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
4964 #address-cells = <3>;
4965 #size-cells = <2>;
4967 num-lanes = <8>;
4968 num-viewport = <8>;
4969 linux,pci-domain = <5>;
4972 clock-names = "core";
4976 reset-names = "apb", "core";
4980 interrupt-names = "intr", "msi";
4982 #interrupt-cells = <1>;
4983 interrupt-map-mask = <0 0 0 0>;
4984 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4988 nvidia,aspm-cmrt-us = <60>;
4989 nvidia,aspm-pwr-on-t-us = <20>;
4990 nvidia,aspm-l0s-entrance-latency-us = <3>;
4992 bus-range = <0x0 0xff>;
4995 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5000 interconnect-names = "dma-mem", "write";
5001 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5002 iommu-map-mask = <0x0>;
5003 dma-coherent;
5008 pcie-ep@141a0000 {
5009 compatible = "nvidia,tegra234-pcie-ep";
5010 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
5015 reg-names = "appl", "atu_dma", "dbi", "addr_space";
5017 num-lanes = <8>;
5020 clock-names = "core";
5024 reset-names = "apb", "core";
5027 interrupt-names = "intr";
5031 nvidia,enable-ext-refclk;
5032 nvidia,aspm-cmrt-us = <60>;
5033 nvidia,aspm-pwr-on-t-us = <20>;
5034 nvidia,aspm-l0s-entrance-latency-us = <3>;
5038 interconnect-names = "dma-mem", "write";
5039 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
5040 iommu-map-mask = <0x0>;
5041 dma-coherent;
5047 compatible = "nvidia,tegra234-pcie";
5048 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5054 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
5056 #address-cells = <3>;
5057 #size-cells = <2>;
5059 num-lanes = <4>;
5060 num-viewport = <8>;
5061 linux,pci-domain = <6>;
5064 clock-names = "core";
5068 reset-names = "apb", "core";
5072 interrupt-names = "intr", "msi";
5074 #interrupt-cells = <1>;
5075 interrupt-map-mask = <0 0 0 0>;
5076 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
5080 nvidia,aspm-cmrt-us = <60>;
5081 nvidia,aspm-pwr-on-t-us = <20>;
5082 nvidia,aspm-l0s-entrance-latency-us = <3>;
5084 bus-range = <0x0 0xff>;
5087 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5092 interconnect-names = "dma-mem", "write";
5093 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5094 iommu-map-mask = <0x0>;
5095 dma-coherent;
5100 pcie-ep@141c0000 {
5101 compatible = "nvidia,tegra234-pcie-ep";
5102 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
5107 reg-names = "appl", "atu_dma", "dbi", "addr_space";
5109 num-lanes = <4>;
5112 clock-names = "core";
5116 reset-names = "apb", "core";
5119 interrupt-names = "intr";
5123 nvidia,enable-ext-refclk;
5124 nvidia,aspm-cmrt-us = <60>;
5125 nvidia,aspm-pwr-on-t-us = <20>;
5126 nvidia,aspm-l0s-entrance-latency-us = <3>;
5130 interconnect-names = "dma-mem", "write";
5131 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
5132 iommu-map-mask = <0x0>;
5133 dma-coherent;
5139 compatible = "nvidia,tegra234-pcie";
5140 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5146 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
5148 #address-cells = <3>;
5149 #size-cells = <2>;
5151 num-lanes = <8>;
5152 num-viewport = <8>;
5153 linux,pci-domain = <7>;
5156 clock-names = "core";
5160 reset-names = "apb", "core";
5164 interrupt-names = "intr", "msi";
5166 #interrupt-cells = <1>;
5167 interrupt-map-mask = <0 0 0 0>;
5168 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
5172 nvidia,aspm-cmrt-us = <60>;
5173 nvidia,aspm-pwr-on-t-us = <20>;
5174 nvidia,aspm-l0s-entrance-latency-us = <3>;
5176 bus-range = <0x0 0xff>;
5179 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
5184 interconnect-names = "dma-mem", "write";
5185 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5186 iommu-map-mask = <0x0>;
5187 dma-coherent;
5192 pcie-ep@141e0000 {
5193 compatible = "nvidia,tegra234-pcie-ep";
5194 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
5199 reg-names = "appl", "atu_dma", "dbi", "addr_space";
5201 num-lanes = <8>;
5204 clock-names = "core";
5208 reset-names = "apb", "core";
5211 interrupt-names = "intr";
5215 nvidia,enable-ext-refclk;
5216 nvidia,aspm-cmrt-us = <60>;
5217 nvidia,aspm-pwr-on-t-us = <20>;
5218 nvidia,aspm-l0s-entrance-latency-us = <3>;
5222 interconnect-names = "dma-mem", "write";
5223 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
5224 iommu-map-mask = <0x0>;
5225 dma-coherent;
5232 compatible = "nvidia,tegra234-sysram", "mmio-sram";
5235 #address-cells = <1>;
5236 #size-cells = <1>;
5239 no-memory-wc;
5243 label = "cpu-bpmp-tx";
5249 label = "cpu-bpmp-rx";
5255 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
5259 #clock-cells = <1>;
5260 #reset-cells = <1>;
5261 #power-domain-cells = <1>;
5266 interconnect-names = "read", "write", "dma-mem", "dma-write";
5270 compatible = "nvidia,tegra186-bpmp-i2c";
5271 nvidia,bpmp-bus-id = <5>;
5272 #address-cells = <1>;
5273 #size-cells = <0>;
5277 compatible = "nvidia,tegra186-bpmp-thermal";
5278 #thermal-sensor-cells = <1>;
5283 #address-cells = <1>;
5284 #size-cells = <0>;
5287 compatible = "arm,cortex-a78";
5291 enable-method = "psci";
5293 operating-points-v2 = <&cl0_opp_tbl>;
5296 i-cache-size = <65536>;
5297 i-cache-line-size = <64>;
5298 i-cache-sets = <256>;
5299 d-cache-size = <65536>;
5300 d-cache-line-size = <64>;
5301 d-cache-sets = <256>;
5302 next-level-cache = <&l2c0_0>;
5306 compatible = "arm,cortex-a78";
5310 enable-method = "psci";
5312 operating-points-v2 = <&cl0_opp_tbl>;
5315 i-cache-size = <65536>;
5316 i-cache-line-size = <64>;
5317 i-cache-sets = <256>;
5318 d-cache-size = <65536>;
5319 d-cache-line-size = <64>;
5320 d-cache-sets = <256>;
5321 next-level-cache = <&l2c0_1>;
5325 compatible = "arm,cortex-a78";
5329 enable-method = "psci";
5331 operating-points-v2 = <&cl0_opp_tbl>;
5334 i-cache-size = <65536>;
5335 i-cache-line-size = <64>;
5336 i-cache-sets = <256>;
5337 d-cache-size = <65536>;
5338 d-cache-line-size = <64>;
5339 d-cache-sets = <256>;
5340 next-level-cache = <&l2c0_2>;
5344 compatible = "arm,cortex-a78";
5348 enable-method = "psci";
5350 operating-points-v2 = <&cl0_opp_tbl>;
5353 i-cache-size = <65536>;
5354 i-cache-line-size = <64>;
5355 i-cache-sets = <256>;
5356 d-cache-size = <65536>;
5357 d-cache-line-size = <64>;
5358 d-cache-sets = <256>;
5359 next-level-cache = <&l2c0_3>;
5363 compatible = "arm,cortex-a78";
5367 enable-method = "psci";
5369 operating-points-v2 = <&cl1_opp_tbl>;
5372 i-cache-size = <65536>;
5373 i-cache-line-size = <64>;
5374 i-cache-sets = <256>;
5375 d-cache-size = <65536>;
5376 d-cache-line-size = <64>;
5377 d-cache-sets = <256>;
5378 next-level-cache = <&l2c1_0>;
5382 compatible = "arm,cortex-a78";
5386 enable-method = "psci";
5388 operating-points-v2 = <&cl1_opp_tbl>;
5391 i-cache-size = <65536>;
5392 i-cache-line-size = <64>;
5393 i-cache-sets = <256>;
5394 d-cache-size = <65536>;
5395 d-cache-line-size = <64>;
5396 d-cache-sets = <256>;
5397 next-level-cache = <&l2c1_1>;
5401 compatible = "arm,cortex-a78";
5405 enable-method = "psci";
5407 operating-points-v2 = <&cl1_opp_tbl>;
5410 i-cache-size = <65536>;
5411 i-cache-line-size = <64>;
5412 i-cache-sets = <256>;
5413 d-cache-size = <65536>;
5414 d-cache-line-size = <64>;
5415 d-cache-sets = <256>;
5416 next-level-cache = <&l2c1_2>;
5420 compatible = "arm,cortex-a78";
5424 enable-method = "psci";
5426 operating-points-v2 = <&cl1_opp_tbl>;
5429 i-cache-size = <65536>;
5430 i-cache-line-size = <64>;
5431 i-cache-sets = <256>;
5432 d-cache-size = <65536>;
5433 d-cache-line-size = <64>;
5434 d-cache-sets = <256>;
5435 next-level-cache = <&l2c1_3>;
5439 compatible = "arm,cortex-a78";
5443 enable-method = "psci";
5445 operating-points-v2 = <&cl2_opp_tbl>;
5448 i-cache-size = <65536>;
5449 i-cache-line-size = <64>;
5450 i-cache-sets = <256>;
5451 d-cache-size = <65536>;
5452 d-cache-line-size = <64>;
5453 d-cache-sets = <256>;
5454 next-level-cache = <&l2c2_0>;
5458 compatible = "arm,cortex-a78";
5462 enable-method = "psci";
5464 operating-points-v2 = <&cl2_opp_tbl>;
5467 i-cache-size = <65536>;
5468 i-cache-line-size = <64>;
5469 i-cache-sets = <256>;
5470 d-cache-size = <65536>;
5471 d-cache-line-size = <64>;
5472 d-cache-sets = <256>;
5473 next-level-cache = <&l2c2_1>;
5477 compatible = "arm,cortex-a78";
5481 enable-method = "psci";
5483 operating-points-v2 = <&cl2_opp_tbl>;
5486 i-cache-size = <65536>;
5487 i-cache-line-size = <64>;
5488 i-cache-sets = <256>;
5489 d-cache-size = <65536>;
5490 d-cache-line-size = <64>;
5491 d-cache-sets = <256>;
5492 next-level-cache = <&l2c2_2>;
5496 compatible = "arm,cortex-a78";
5500 enable-method = "psci";
5502 operating-points-v2 = <&cl2_opp_tbl>;
5505 i-cache-size = <65536>;
5506 i-cache-line-size = <64>;
5507 i-cache-sets = <256>;
5508 d-cache-size = <65536>;
5509 d-cache-line-size = <64>;
5510 d-cache-sets = <256>;
5511 next-level-cache = <&l2c2_3>;
5514 cpu-map {
5570 l2c0_0: l2-cache00 {
5572 cache-size = <262144>;
5573 cache-line-size = <64>;
5574 cache-sets = <512>;
5575 cache-unified;
5576 cache-level = <2>;
5577 next-level-cache = <&l3c0>;
5580 l2c0_1: l2-cache01 {
5582 cache-size = <262144>;
5583 cache-line-size = <64>;
5584 cache-sets = <512>;
5585 cache-unified;
5586 cache-level = <2>;
5587 next-level-cache = <&l3c0>;
5590 l2c0_2: l2-cache02 {
5592 cache-size = <262144>;
5593 cache-line-size = <64>;
5594 cache-sets = <512>;
5595 cache-unified;
5596 cache-level = <2>;
5597 next-level-cache = <&l3c0>;
5600 l2c0_3: l2-cache03 {
5602 cache-size = <262144>;
5603 cache-line-size = <64>;
5604 cache-sets = <512>;
5605 cache-unified;
5606 cache-level = <2>;
5607 next-level-cache = <&l3c0>;
5610 l2c1_0: l2-cache10 {
5612 cache-size = <262144>;
5613 cache-line-size = <64>;
5614 cache-sets = <512>;
5615 cache-unified;
5616 cache-level = <2>;
5617 next-level-cache = <&l3c1>;
5620 l2c1_1: l2-cache11 {
5622 cache-size = <262144>;
5623 cache-line-size = <64>;
5624 cache-sets = <512>;
5625 cache-unified;
5626 cache-level = <2>;
5627 next-level-cache = <&l3c1>;
5630 l2c1_2: l2-cache12 {
5632 cache-size = <262144>;
5633 cache-line-size = <64>;
5634 cache-sets = <512>;
5635 cache-unified;
5636 cache-level = <2>;
5637 next-level-cache = <&l3c1>;
5640 l2c1_3: l2-cache13 {
5642 cache-size = <262144>;
5643 cache-line-size = <64>;
5644 cache-sets = <512>;
5645 cache-unified;
5646 cache-level = <2>;
5647 next-level-cache = <&l3c1>;
5650 l2c2_0: l2-cache20 {
5652 cache-size = <262144>;
5653 cache-line-size = <64>;
5654 cache-sets = <512>;
5655 cache-unified;
5656 cache-level = <2>;
5657 next-level-cache = <&l3c2>;
5660 l2c2_1: l2-cache21 {
5662 cache-size = <262144>;
5663 cache-line-size = <64>;
5664 cache-sets = <512>;
5665 cache-unified;
5666 cache-level = <2>;
5667 next-level-cache = <&l3c2>;
5670 l2c2_2: l2-cache22 {
5672 cache-size = <262144>;
5673 cache-line-size = <64>;
5674 cache-sets = <512>;
5675 cache-unified;
5676 cache-level = <2>;
5677 next-level-cache = <&l3c2>;
5680 l2c2_3: l2-cache23 {
5682 cache-size = <262144>;
5683 cache-line-size = <64>;
5684 cache-sets = <512>;
5685 cache-unified;
5686 cache-level = <2>;
5687 next-level-cache = <&l3c2>;
5690 l3c0: l3-cache0 {
5692 cache-unified;
5693 cache-size = <2097152>;
5694 cache-line-size = <64>;
5695 cache-sets = <2048>;
5696 cache-level = <3>;
5699 l3c1: l3-cache1 {
5701 cache-unified;
5702 cache-size = <2097152>;
5703 cache-line-size = <64>;
5704 cache-sets = <2048>;
5705 cache-level = <3>;
5708 l3c2: l3-cache2 {
5710 cache-unified;
5711 cache-size = <2097152>;
5712 cache-line-size = <64>;
5713 cache-sets = <2048>;
5714 cache-level = <3>;
5718 dsu-pmu0 {
5719 compatible = "arm,dsu-pmu";
5724 dsu-pmu1 {
5725 compatible = "arm,dsu-pmu";
5730 dsu-pmu2 {
5731 compatible = "arm,dsu-pmu";
5737 compatible = "arm,cortex-a78-pmu";
5743 compatible = "arm,psci-1.0";
5749 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
5752 mbox-names = "rx", "tx";
5761 clock-names = "pll_a", "plla_out0";
5762 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
5765 assigned-clock-parents = <0>,
5770 thermal-zones {
5771 cpu-thermal {
5772 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
5776 gpu-thermal {
5777 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
5781 cv0-thermal {
5782 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
5786 cv1-thermal {
5787 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
5791 cv2-thermal {
5792 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
5796 soc0-thermal {
5797 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
5801 soc1-thermal {
5802 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
5806 soc2-thermal {
5807 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
5811 tj-thermal {
5812 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
5818 compatible = "arm,armv8-timer";
5823 interrupt-parent = <&gic>;
5824 always-on;
5827 cl0_opp_tbl: opp-table-cluster0 {
5828 compatible = "operating-points-v2";
5829 opp-shared;
5831 cl0_ch1_opp1: opp-115200000 {
5832 opp-hz = /bits/ 64 <115200000>;
5833 opp-peak-kBps = <816000>;
5836 cl0_ch1_opp2: opp-192000000 {
5837 opp-hz = /bits/ 64 <192000000>;
5838 opp-peak-kBps = <816000>;
5841 cl0_ch1_opp3: opp-268800000 {
5842 opp-hz = /bits/ 64 <268800000>;
5843 opp-peak-kBps = <816000>;
5846 cl0_ch1_opp4: opp-345600000 {
5847 opp-hz = /bits/ 64 <345600000>;
5848 opp-peak-kBps = <816000>;
5851 cl0_ch1_opp5: opp-422400000 {
5852 opp-hz = /bits/ 64 <422400000>;
5853 opp-peak-kBps = <816000>;
5856 cl0_ch1_opp6: opp-499200000 {
5857 opp-hz = /bits/ 64 <499200000>;
5858 opp-peak-kBps = <816000>;
5861 cl0_ch1_opp7: opp-576000000 {
5862 opp-hz = /bits/ 64 <576000000>;
5863 opp-peak-kBps = <816000>;
5866 cl0_ch1_opp8: opp-652800000 {
5867 opp-hz = /bits/ 64 <652800000>;
5868 opp-peak-kBps = <816000>;
5871 cl0_ch1_opp9: opp-729600000 {
5872 opp-hz = /bits/ 64 <729600000>;
5873 opp-peak-kBps = <816000>;
5876 cl0_ch1_opp10: opp-806400000 {
5877 opp-hz = /bits/ 64 <806400000>;
5878 opp-peak-kBps = <816000>;
5881 cl0_ch1_opp11: opp-883200000 {
5882 opp-hz = /bits/ 64 <883200000>;
5883 opp-peak-kBps = <816000>;
5886 cl0_ch1_opp12: opp-960000000 {
5887 opp-hz = /bits/ 64 <960000000>;
5888 opp-peak-kBps = <816000>;
5891 cl0_ch1_opp13: opp-1036800000 {
5892 opp-hz = /bits/ 64 <1036800000>;
5893 opp-peak-kBps = <816000>;
5896 cl0_ch1_opp14: opp-1113600000 {
5897 opp-hz = /bits/ 64 <1113600000>;
5898 opp-peak-kBps = <1632000>;
5901 cl0_ch1_opp15: opp-1190400000 {
5902 opp-hz = /bits/ 64 <1190400000>;
5903 opp-peak-kBps = <1632000>;
5906 cl0_ch1_opp16: opp-1267200000 {
5907 opp-hz = /bits/ 64 <1267200000>;
5908 opp-peak-kBps = <1632000>;
5911 cl0_ch1_opp17: opp-1344000000 {
5912 opp-hz = /bits/ 64 <1344000000>;
5913 opp-peak-kBps = <1632000>;
5916 cl0_ch1_opp18: opp-1420800000 {
5917 opp-hz = /bits/ 64 <1420800000>;
5918 opp-peak-kBps = <1632000>;
5921 cl0_ch1_opp19: opp-1497600000 {
5922 opp-hz = /bits/ 64 <1497600000>;
5923 opp-peak-kBps = <3200000>;
5926 cl0_ch1_opp20: opp-1574400000 {
5927 opp-hz = /bits/ 64 <1574400000>;
5928 opp-peak-kBps = <3200000>;
5931 cl0_ch1_opp21: opp-1651200000 {
5932 opp-hz = /bits/ 64 <1651200000>;
5933 opp-peak-kBps = <3200000>;
5936 cl0_ch1_opp22: opp-1728000000 {
5937 opp-hz = /bits/ 64 <1728000000>;
5938 opp-peak-kBps = <3200000>;
5941 cl0_ch1_opp23: opp-1804800000 {
5942 opp-hz = /bits/ 64 <1804800000>;
5943 opp-peak-kBps = <3200000>;
5946 cl0_ch1_opp24: opp-1881600000 {
5947 opp-hz = /bits/ 64 <1881600000>;
5948 opp-peak-kBps = <3200000>;
5951 cl0_ch1_opp25: opp-1958400000 {
5952 opp-hz = /bits/ 64 <1958400000>;
5953 opp-peak-kBps = <3200000>;
5956 cl0_ch1_opp26: opp-2035200000 {
5957 opp-hz = /bits/ 64 <2035200000>;
5958 opp-peak-kBps = <3200000>;
5961 cl0_ch1_opp27: opp-2112000000 {
5962 opp-hz = /bits/ 64 <2112000000>;
5963 opp-peak-kBps = <6400000>;
5966 cl0_ch1_opp28: opp-2188800000 {
5967 opp-hz = /bits/ 64 <2188800000>;
5968 opp-peak-kBps = <6400000>;
5971 cl0_ch1_opp29: opp-2201600000 {
5972 opp-hz = /bits/ 64 <2201600000>;
5973 opp-peak-kBps = <6400000>;
5977 cl1_opp_tbl: opp-table-cluster1 {
5978 compatible = "operating-points-v2";
5979 opp-shared;
5981 cl1_ch1_opp1: opp-115200000 {
5982 opp-hz = /bits/ 64 <115200000>;
5983 opp-peak-kBps = <816000>;
5986 cl1_ch1_opp2: opp-192000000 {
5987 opp-hz = /bits/ 64 <192000000>;
5988 opp-peak-kBps = <816000>;
5991 cl1_ch1_opp3: opp-268800000 {
5992 opp-hz = /bits/ 64 <268800000>;
5993 opp-peak-kBps = <816000>;
5996 cl1_ch1_opp4: opp-345600000 {
5997 opp-hz = /bits/ 64 <345600000>;
5998 opp-peak-kBps = <816000>;
6001 cl1_ch1_opp5: opp-422400000 {
6002 opp-hz = /bits/ 64 <422400000>;
6003 opp-peak-kBps = <816000>;
6006 cl1_ch1_opp6: opp-499200000 {
6007 opp-hz = /bits/ 64 <499200000>;
6008 opp-peak-kBps = <816000>;
6011 cl1_ch1_opp7: opp-576000000 {
6012 opp-hz = /bits/ 64 <576000000>;
6013 opp-peak-kBps = <816000>;
6016 cl1_ch1_opp8: opp-652800000 {
6017 opp-hz = /bits/ 64 <652800000>;
6018 opp-peak-kBps = <816000>;
6021 cl1_ch1_opp9: opp-729600000 {
6022 opp-hz = /bits/ 64 <729600000>;
6023 opp-peak-kBps = <816000>;
6026 cl1_ch1_opp10: opp-806400000 {
6027 opp-hz = /bits/ 64 <806400000>;
6028 opp-peak-kBps = <816000>;
6031 cl1_ch1_opp11: opp-883200000 {
6032 opp-hz = /bits/ 64 <883200000>;
6033 opp-peak-kBps = <816000>;
6036 cl1_ch1_opp12: opp-960000000 {
6037 opp-hz = /bits/ 64 <960000000>;
6038 opp-peak-kBps = <816000>;
6041 cl1_ch1_opp13: opp-1036800000 {
6042 opp-hz = /bits/ 64 <1036800000>;
6043 opp-peak-kBps = <816000>;
6046 cl1_ch1_opp14: opp-1113600000 {
6047 opp-hz = /bits/ 64 <1113600000>;
6048 opp-peak-kBps = <1632000>;
6051 cl1_ch1_opp15: opp-1190400000 {
6052 opp-hz = /bits/ 64 <1190400000>;
6053 opp-peak-kBps = <1632000>;
6056 cl1_ch1_opp16: opp-1267200000 {
6057 opp-hz = /bits/ 64 <1267200000>;
6058 opp-peak-kBps = <1632000>;
6061 cl1_ch1_opp17: opp-1344000000 {
6062 opp-hz = /bits/ 64 <1344000000>;
6063 opp-peak-kBps = <1632000>;
6066 cl1_ch1_opp18: opp-1420800000 {
6067 opp-hz = /bits/ 64 <1420800000>;
6068 opp-peak-kBps = <1632000>;
6071 cl1_ch1_opp19: opp-1497600000 {
6072 opp-hz = /bits/ 64 <1497600000>;
6073 opp-peak-kBps = <3200000>;
6076 cl1_ch1_opp20: opp-1574400000 {
6077 opp-hz = /bits/ 64 <1574400000>;
6078 opp-peak-kBps = <3200000>;
6081 cl1_ch1_opp21: opp-1651200000 {
6082 opp-hz = /bits/ 64 <1651200000>;
6083 opp-peak-kBps = <3200000>;
6086 cl1_ch1_opp22: opp-1728000000 {
6087 opp-hz = /bits/ 64 <1728000000>;
6088 opp-peak-kBps = <3200000>;
6091 cl1_ch1_opp23: opp-1804800000 {
6092 opp-hz = /bits/ 64 <1804800000>;
6093 opp-peak-kBps = <3200000>;
6096 cl1_ch1_opp24: opp-1881600000 {
6097 opp-hz = /bits/ 64 <1881600000>;
6098 opp-peak-kBps = <3200000>;
6101 cl1_ch1_opp25: opp-1958400000 {
6102 opp-hz = /bits/ 64 <1958400000>;
6103 opp-peak-kBps = <3200000>;
6106 cl1_ch1_opp26: opp-2035200000 {
6107 opp-hz = /bits/ 64 <2035200000>;
6108 opp-peak-kBps = <3200000>;
6111 cl1_ch1_opp27: opp-2112000000 {
6112 opp-hz = /bits/ 64 <2112000000>;
6113 opp-peak-kBps = <6400000>;
6116 cl1_ch1_opp28: opp-2188800000 {
6117 opp-hz = /bits/ 64 <2188800000>;
6118 opp-peak-kBps = <6400000>;
6121 cl1_ch1_opp29: opp-2201600000 {
6122 opp-hz = /bits/ 64 <2201600000>;
6123 opp-peak-kBps = <6400000>;
6127 cl2_opp_tbl: opp-table-cluster2 {
6128 compatible = "operating-points-v2";
6129 opp-shared;
6131 cl2_ch1_opp1: opp-115200000 {
6132 opp-hz = /bits/ 64 <115200000>;
6133 opp-peak-kBps = <816000>;
6136 cl2_ch1_opp2: opp-192000000 {
6137 opp-hz = /bits/ 64 <192000000>;
6138 opp-peak-kBps = <816000>;
6141 cl2_ch1_opp3: opp-268800000 {
6142 opp-hz = /bits/ 64 <268800000>;
6143 opp-peak-kBps = <816000>;
6146 cl2_ch1_opp4: opp-345600000 {
6147 opp-hz = /bits/ 64 <345600000>;
6148 opp-peak-kBps = <816000>;
6151 cl2_ch1_opp5: opp-422400000 {
6152 opp-hz = /bits/ 64 <422400000>;
6153 opp-peak-kBps = <816000>;
6156 cl2_ch1_opp6: opp-499200000 {
6157 opp-hz = /bits/ 64 <499200000>;
6158 opp-peak-kBps = <816000>;
6161 cl2_ch1_opp7: opp-576000000 {
6162 opp-hz = /bits/ 64 <576000000>;
6163 opp-peak-kBps = <816000>;
6166 cl2_ch1_opp8: opp-652800000 {
6167 opp-hz = /bits/ 64 <652800000>;
6168 opp-peak-kBps = <816000>;
6171 cl2_ch1_opp9: opp-729600000 {
6172 opp-hz = /bits/ 64 <729600000>;
6173 opp-peak-kBps = <816000>;
6176 cl2_ch1_opp10: opp-806400000 {
6177 opp-hz = /bits/ 64 <806400000>;
6178 opp-peak-kBps = <816000>;
6181 cl2_ch1_opp11: opp-883200000 {
6182 opp-hz = /bits/ 64 <883200000>;
6183 opp-peak-kBps = <816000>;
6186 cl2_ch1_opp12: opp-960000000 {
6187 opp-hz = /bits/ 64 <960000000>;
6188 opp-peak-kBps = <816000>;
6191 cl2_ch1_opp13: opp-1036800000 {
6192 opp-hz = /bits/ 64 <1036800000>;
6193 opp-peak-kBps = <816000>;
6196 cl2_ch1_opp14: opp-1113600000 {
6197 opp-hz = /bits/ 64 <1113600000>;
6198 opp-peak-kBps = <1632000>;
6201 cl2_ch1_opp15: opp-1190400000 {
6202 opp-hz = /bits/ 64 <1190400000>;
6203 opp-peak-kBps = <1632000>;
6206 cl2_ch1_opp16: opp-1267200000 {
6207 opp-hz = /bits/ 64 <1267200000>;
6208 opp-peak-kBps = <1632000>;
6211 cl2_ch1_opp17: opp-1344000000 {
6212 opp-hz = /bits/ 64 <1344000000>;
6213 opp-peak-kBps = <1632000>;
6216 cl2_ch1_opp18: opp-1420800000 {
6217 opp-hz = /bits/ 64 <1420800000>;
6218 opp-peak-kBps = <1632000>;
6221 cl2_ch1_opp19: opp-1497600000 {
6222 opp-hz = /bits/ 64 <1497600000>;
6223 opp-peak-kBps = <3200000>;
6226 cl2_ch1_opp20: opp-1574400000 {
6227 opp-hz = /bits/ 64 <1574400000>;
6228 opp-peak-kBps = <3200000>;
6231 cl2_ch1_opp21: opp-1651200000 {
6232 opp-hz = /bits/ 64 <1651200000>;
6233 opp-peak-kBps = <3200000>;
6236 cl2_ch1_opp22: opp-1728000000 {
6237 opp-hz = /bits/ 64 <1728000000>;
6238 opp-peak-kBps = <3200000>;
6241 cl2_ch1_opp23: opp-1804800000 {
6242 opp-hz = /bits/ 64 <1804800000>;
6243 opp-peak-kBps = <3200000>;
6246 cl2_ch1_opp24: opp-1881600000 {
6247 opp-hz = /bits/ 64 <1881600000>;
6248 opp-peak-kBps = <3200000>;
6251 cl2_ch1_opp25: opp-1958400000 {
6252 opp-hz = /bits/ 64 <1958400000>;
6253 opp-peak-kBps = <3200000>;
6256 cl2_ch1_opp26: opp-2035200000 {
6257 opp-hz = /bits/ 64 <2035200000>;
6258 opp-peak-kBps = <3200000>;
6261 cl2_ch1_opp27: opp-2112000000 {
6262 opp-hz = /bits/ 64 <2112000000>;
6263 opp-peak-kBps = <6400000>;
6266 cl2_ch1_opp28: opp-2188800000 {
6267 opp-hz = /bits/ 64 <2188800000>;
6268 opp-peak-kBps = <6400000>;
6271 cl2_ch1_opp29: opp-2201600000 {
6272 opp-hz = /bits/ 64 <2201600000>;
6273 opp-peak-kBps = <6400000>;