Lines Matching +full:0 +full:xc2f1000
20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
107 <0x0 0x23b0000 0x0 0x1000>,
108 <0x0 0x23c0000 0x0 0x1000>,
109 <0x0 0x23d0000 0x0 0x1000>,
110 <0x0 0x23e0000 0x0 0x1000>;
116 reg = <0x0 0x2430000 0x0 0x17000>;
146 reg = <0x0 0x02490000 0x0 0x10000>;
164 snps,burst-map = <0x7>;
172 reg = <0x0 0x2600000 0x0 0x210000>;
210 dma-channel-mask = <0xfffffffe>;
225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
230 reg = <0x0 0x02900800 0x0 0x800>;
240 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
245 reg = <0x0 0x2901000 0x0 0x100>;
259 reg = <0x0 0x2901100 0x0 0x100>;
273 reg = <0x0 0x2901200 0x0 0x100>;
287 reg = <0x0 0x2901300 0x0 0x100>;
301 reg = <0x0 0x2901400 0x0 0x100>;
315 reg = <0x0 0x2901500 0x0 0x100>;
329 reg = <0x0 0x2902000 0x0 0x200>;
337 reg = <0x0 0x2902200 0x0 0x200>;
345 reg = <0x0 0x2902400 0x0 0x200>;
353 reg = <0x0 0x2902600 0x0 0x200>;
360 reg = <0x0 0x2903000 0x0 0x100>;
367 reg = <0x0 0x2903100 0x0 0x100>;
374 reg = <0x0 0x2903200 0x0 0x100>;
381 reg = <0x0 0x2903300 0x0 0x100>;
389 reg = <0x0 0x2903800 0x0 0x100>;
397 reg = <0x0 0x2903900 0x0 0x100>;
405 reg = <0x0 0x2903a00 0x0 0x100>;
413 reg = <0x0 0x2903b00 0x0 0x100>;
421 reg = <0x0 0x2904000 0x0 0x100>;
434 reg = <0x0 0x2904100 0x0 0x100>;
447 reg = <0x0 0x2904200 0x0 0x100>;
460 reg = <0x0 0x2904300 0x0 0x100>;
473 reg = <0x0 0x2905000 0x0 0x100>;
486 reg = <0x0 0x2905100 0x0 0x100>;
499 reg = <0x0 0x2908000 0x0 0x100>;
510 reg = <0x0 0x2908100 0x0 0x100>;
516 reg = <0x0 0x2908200 0x0 0x200>;
523 reg = <0x0 0x290a000 0x0 0x200>;
531 reg = <0x0 0x290a200 0x0 0x200>;
539 reg = <0x0 0x290bb00 0x0 0x800>;
547 reg = <0x0 0x0290f000 0x0 0x1000>;
598 reg = <0x0 0x2910000 0x0 0x2000>;
607 reg = <0x0 0x02930000 0x0 0x20000>;
609 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
652 reg = <0x0 0x02a41000 0x0 0x1000>,
653 <0x0 0x02a42000 0x0 0x2000>;
665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
666 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
667 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
668 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
669 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
670 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
671 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
672 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
673 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
674 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
675 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
676 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
677 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
678 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
679 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
680 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
681 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
682 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
692 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
693 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
694 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
709 * Limit the DMA range for memory clients to [38:0].
711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
715 reg = <0x0 0x02c60000 0x0 0x90000>,
716 <0x0 0x01780000 0x0 0x80000>;
721 #interconnect-cells = <0>;
729 reg = <0x0 0x03010000 0x0 0x000e0000>;
730 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
745 reg = <0x0 0x03100000 0x0 0x40>;
757 reg = <0x0 0x03110000 0x0 0x40>;
769 reg = <0x0 0x03130000 0x0 0x40>;
781 reg = <0x0 0x03140000 0x0 0x40>;
793 reg = <0x0 0x03150000 0x0 0x40>;
805 reg = <0x0 0x03160000 0x0 0x10000>;
808 #size-cells = <0>;
820 reg = <0x0 0x03170000 0x0 0x40>;
832 reg = <0x0 0x03180000 0x0 0x10000>;
835 #size-cells = <0>;
848 reg = <0x0 0x03190000 0x0 0x10000>;
851 #size-cells = <0>;
856 pinctrl-0 = <&state_dpaux1_i2c>;
867 reg = <0x0 0x031b0000 0x0 0x10000>;
870 #size-cells = <0>;
875 pinctrl-0 = <&state_dpaux0_i2c>;
886 reg = <0x0 0x031c0000 0x0 0x10000>;
889 #size-cells = <0>;
894 pinctrl-0 = <&state_dpaux2_i2c>;
905 reg = <0x0 0x031e0000 0x0 0x10000>;
908 #size-cells = <0>;
913 pinctrl-0 = <&state_dpaux3_i2c>;
923 reg = <0x0 0x3270000 0x0 0x1000>;
926 #size-cells = <0>;
937 reg = <0x0 0x3280000 0x0 0x10000>;
948 reg = <0x0 0x3290000 0x0 0x10000>;
959 reg = <0x0 0x32a0000 0x0 0x10000>;
970 reg = <0x0 0x32c0000 0x0 0x10000>;
981 reg = <0x0 0x32d0000 0x0 0x10000>;
992 reg = <0x0 0x32e0000 0x0 0x10000>;
1003 reg = <0x0 0x32f0000 0x0 0x10000>;
1013 reg = <0x0 0x3300000 0x0 0x1000>;
1016 #size-cells = <0>;
1026 reg = <0x0 0x03400000 0x0 0x10000>;
1043 pinctrl-0 = <&sdmmc1_3v3>;
1046 <0x07>;
1048 <0x07>;
1049 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1051 <0x07>;
1052 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1053 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1054 nvidia,default-tap = <0x9>;
1055 nvidia,default-trim = <0x5>;
1065 reg = <0x0 0x03440000 0x0 0x10000>;
1082 pinctrl-0 = <&sdmmc3_3v3>;
1084 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1085 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1086 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1088 <0x07>;
1089 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1091 <0x07>;
1092 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1093 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1094 nvidia,default-tap = <0x9>;
1095 nvidia,default-trim = <0x5>;
1105 reg = <0x0 0x03460000 0x0 0x10000>;
1120 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1121 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1122 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1124 <0x0a>;
1125 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1127 <0x0a>;
1128 nvidia,default-tap = <0x8>;
1129 nvidia,default-trim = <0x14>;
1142 reg = <0x0 0x3510000 0x0 0x10000>;
1161 reg = <0x0 0x03520000 0x0 0x1000>,
1162 <0x0 0x03540000 0x0 0x1000>;
1177 usb2-0 {
1180 #phy-cells = <0>;
1186 #phy-cells = <0>;
1192 #phy-cells = <0>;
1198 #phy-cells = <0>;
1205 usb3-0 {
1208 #phy-cells = <0>;
1214 #phy-cells = <0>;
1220 #phy-cells = <0>;
1226 #phy-cells = <0>;
1233 usb2-0 {
1249 usb3-0 {
1269 reg = <0x0 0x03550000 0x0 0x8000>,
1270 <0x0 0x03558000 0x0 0x1000>;
1292 reg = <0x0 0x03610000 0x0 0x40000>,
1293 <0x0 0x03600000 0x0 0x10000>;
1327 reg = <0x0 0x03820000 0x0 0x10000>;
1336 reg = <0x0 0x03881000 0x0 0x1000>,
1337 <0x0 0x03882000 0x0 0x2000>,
1338 <0x0 0x03884000 0x0 0x2000>,
1339 <0x0 0x03886000 0x0 0x2000>;
1347 reg = <0x0 0x03960000 0x0 0x10000>;
1356 reg = <0x0 0x3aa0000 0x0 0x10000>;
1366 reg = <0x0 0x03c00000 0x0 0xa0000>;
1384 reg = <0x0 0x03e10000 0x0 0x10000>;
1387 #phy-cells = <0>;
1392 reg = <0x0 0x03e20000 0x0 0x10000>;
1395 #phy-cells = <0>;
1400 reg = <0x0 0x03e30000 0x0 0x10000>;
1403 #phy-cells = <0>;
1408 reg = <0x0 0x03e40000 0x0 0x10000>;
1411 #phy-cells = <0>;
1416 reg = <0x0 0x03e50000 0x0 0x10000>;
1419 #phy-cells = <0>;
1424 reg = <0x0 0x03e60000 0x0 0x10000>;
1427 #phy-cells = <0>;
1432 reg = <0x0 0x03e70000 0x0 0x10000>;
1435 #phy-cells = <0>;
1440 reg = <0x0 0x03e80000 0x0 0x10000>;
1443 #phy-cells = <0>;
1448 reg = <0x0 0x03e90000 0x0 0x10000>;
1451 #phy-cells = <0>;
1456 reg = <0x0 0x03ea0000 0x0 0x10000>;
1459 #phy-cells = <0>;
1464 reg = <0x0 0x03eb0000 0x0 0x10000>;
1467 #phy-cells = <0>;
1472 reg = <0x0 0x03ec0000 0x0 0x10000>;
1475 #phy-cells = <0>;
1480 reg = <0x0 0x03ed0000 0x0 0x10000>;
1483 #phy-cells = <0>;
1488 reg = <0x0 0x03ee0000 0x0 0x10000>;
1491 #phy-cells = <0>;
1496 reg = <0x0 0x03ef0000 0x0 0x10000>;
1499 #phy-cells = <0>;
1504 reg = <0x0 0x03f00000 0x0 0x10000>;
1507 #phy-cells = <0>;
1512 reg = <0x0 0x03f10000 0x0 0x10000>;
1515 #phy-cells = <0>;
1520 reg = <0x0 0x03f20000 0x0 0x10000>;
1523 #phy-cells = <0>;
1528 reg = <0x0 0x03f30000 0x0 0x10000>;
1531 #phy-cells = <0>;
1536 reg = <0x0 0x03f40000 0x0 0x10000>;
1539 #phy-cells = <0>;
1544 reg = <0x0 0xb600000 0x0 0x1000>;
1554 reg = <0x0 0xbe00000 0x0 0x1000>;
1564 reg = <0x0 0x0c150000 0x0 0x90000>;
1570 * Shared interrupt 0 is routed only to AON/SPE, so
1579 reg = <0x0 0xc1e0000 0x0 0x10000>;
1589 reg = <0x0 0x0c240000 0x0 0x10000>;
1592 #size-cells = <0>;
1604 reg = <0x0 0x0c250000 0x0 0x10000>;
1607 #size-cells = <0>;
1612 dmas = <&gpcdma 0>, <&gpcdma 0>;
1619 reg = <0x0 0x0c280000 0x0 0x40>;
1631 reg = <0x0 0x0c290000 0x0 0x40>;
1643 reg = <0x0 0x0c2a0000 0x0 0x10000>;
1654 reg = <0x0 0xc2f0000 0x0 0x1000>,
1655 <0x0 0xc2f1000 0x0 0x1000>;
1664 gpio-ranges = <&pinmux_aon 0 0 30>;
1669 reg = <0x0 0xc300000 0x0 0x4000>;
1677 reg = <0x0 0xc340000 0x0 0x10000>;
1687 reg = <0x0 0x0c360000 0x0 0x10000>,
1688 <0x0 0x0c370000 0x0 0x10000>,
1689 <0x0 0x0c380000 0x0 0x10000>,
1690 <0x0 0x0c390000 0x0 0x10000>,
1691 <0x0 0x0c3a0000 0x0 0x10000>;
1720 reg = <0x0 0xc600000 0x0 0x1000>;
1729 reg = <0x0 0xd600000 0x0 0x1000>;
1739 reg = <0x0 0x10000000 0x0 0x800000>;
1805 stream-match-mask = <0x7f80>;
1815 reg = <0x0 0x12000000 0x0 0x800000>,
1816 <0x0 0x11000000 0x0 0x800000>;
1883 stream-match-mask = <0x7f80>;
1893 reg = <0x0 0x13e00000 0x0 0x10000>,
1894 <0x0 0x13e10000 0x0 0x10000>;
1906 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>;
1914 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1925 reg = <0x0 0x15140000 0x0 0x00040000>;
1939 nvidia,host1x-class = <0xf5>;
1944 reg = <0x0 0x15200000 0x0 0x00040000>;
1963 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
1967 reg = <0x0 0x15200000 0x0 0x10000>;
1980 nvidia,head = <0>;
1985 reg = <0x0 0x15210000 0x0 0x10000>;
2003 reg = <0x0 0x15220000 0x0 0x10000>;
2021 reg = <0x0 0x15230000 0x0 0x10000>;
2040 reg = <0x0 0x15340000 0x0 0x00040000>;
2057 reg = <0x0 0x15380000 0x0 0x40000>;
2073 reg = <0x0 0x15480000 0x0 0x00040000>;
2087 nvidia,host1x-class = <0xf0>;
2092 reg = <0x0 0x154c0000 0x0 0x40000>;
2106 nvidia,host1x-class = <0x21>;
2111 reg = <0x0 0x155c0000 0x0 0x10000>;
2139 #size-cells = <0>;
2145 reg = <0x0 0x155d0000 0x0 0x10000>;
2173 #size-cells = <0>;
2179 reg = <0x0 0x155e0000 0x0 0x10000>;
2207 #size-cells = <0>;
2213 reg = <0x0 0x155f0000 0x0 0x10000>;
2241 #size-cells = <0>;
2247 reg = <0x0 0x15a80000 0x0 0x00040000>;
2261 nvidia,host1x-class = <0x22>;
2266 reg = <0x0 0x15b00000 0x0 0x40000>;
2278 pinctrl-0 = <&state_dpaux0_aux>;
2285 nvidia,interface = <0>;
2290 reg = <0x0 0x15b40000 0x0 0x40000>;
2302 pinctrl-0 = <&state_dpaux1_aux>;
2314 reg = <0x0 0x15b80000 0x0 0x40000>;
2326 pinctrl-0 = <&state_dpaux2_aux>;
2338 reg = <0x0 0x15bc0000 0x0 0x40000>;
2350 pinctrl-0 = <&state_dpaux3_aux>;
2364 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2365 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2366 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2367 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2390 interrupt-map-mask = <0 0 0 0>;
2391 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2399 bus-range = <0x0 0xff>;
2401 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2402 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2403 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2408 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2409 iommu-map-mask = <0x0>;
2416 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2417 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2418 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2419 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2442 interrupt-map-mask = <0 0 0 0>;
2443 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2451 bus-range = <0x0 0xff>;
2453 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2454 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2455 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2460 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2461 iommu-map-mask = <0x0>;
2468 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2469 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2470 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2471 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2494 interrupt-map-mask = <0 0 0 0>;
2495 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2503 bus-range = <0x0 0xff>;
2505 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2506 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2507 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2512 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2513 iommu-map-mask = <0x0>;
2520 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2521 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2522 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2523 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2546 interrupt-map-mask = <0 0 0 0>;
2547 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2555 bus-range = <0x0 0xff>;
2557 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2558 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2559 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2564 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2565 iommu-map-mask = <0x0>;
2572 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2573 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2574 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2575 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2603 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2604 iommu-map-mask = <0x0>;
2611 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2612 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2613 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2614 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2623 linux,pci-domain = <0>;
2637 interrupt-map-mask = <0 0 0 0>;
2638 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2640 nvidia,bpmp = <&bpmp 0>;
2646 bus-range = <0x0 0xff>;
2648 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2649 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2650 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2655 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2656 iommu-map-mask = <0x0>;
2663 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2664 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2665 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2666 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2685 nvidia,bpmp = <&bpmp 0>;
2694 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2695 iommu-map-mask = <0x0>;
2702 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2703 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2704 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2705 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2717 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2733 interrupt-map-mask = <0 0 0 0>;
2734 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2740 bus-range = <0x0 0xff>;
2742 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2743 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2744 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2749 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2750 iommu-map-mask = <0x0>;
2757 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2758 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2759 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2760 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2770 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2791 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2792 iommu-map-mask = <0x0>;
2798 reg = <0x0 0x17000000 0x0 0x1000000>,
2799 <0x0 0x18000000 0x0 0x1000000>;
2824 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2833 reg = <0x0 0x40000000 0x0 0x50000>;
2837 ranges = <0x0 0x0 0x40000000 0x50000>;
2842 reg = <0x4e000 0x1000>;
2848 reg = <0x4f000 0x1000>;
2873 #size-cells = <0>;
2886 #size-cells = <0>;
2888 cpu0_0: cpu@0 {
2891 reg = <0x000>;
2905 reg = <0x001>;
2919 reg = <0x100>;
2933 reg = <0x101>;
2947 reg = <0x200>;
2961 reg = <0x201>;
2975 reg = <0x300>;
2989 reg = <0x301>;
3114 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3128 assigned-clock-parents = <0>,