Lines Matching +full:0 +full:x10007000
53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
243 cpu_off = <0x84000002>;
244 cpu_on = <0x84000003>;
249 #clock-cells = <0>;
256 #clock-cells = <0>;
263 #clock-cells = <0>;
264 clock-frequency = <0>;
324 size = <0 0x100000>;
325 alignment = <0 0x10>;
331 reg = <0 0xb7000000 0 0x500000>;
332 alignment = <0x1000>;
359 reg = <0 0x10000000 0 0x1000>;
365 reg = <0 0x10001000 0 0x1000>;
372 reg = <0 0x10003000 0 0x1000>;
379 reg = <0 0x10005000 0 0x1000>;
384 reg = <0 0x1000b000 0 0x1000>;
455 reg = <0 0x10006000 0 0x1000>;
461 #size-cells = <0>;
469 #power-domain-cells = <0>;
476 #power-domain-cells = <0>;
482 #power-domain-cells = <0>;
488 #power-domain-cells = <0>;
496 #power-domain-cells = <0>;
500 #power-domain-cells = <0>;
504 #power-domain-cells = <0>;
511 #size-cells = <0>;
517 #size-cells = <0>;
522 #power-domain-cells = <0>;
533 reg = <0 0x10007000 0 0x100>;
539 reg = <0 0x10008000 0 0x1000>;
547 reg = <0 0x1000d000 0 0x1000>;
558 reg = <0 0x10013000 0 0xbc>;
566 reg = <0 0x10020000 0 0x30000>,
567 <0 0x10050000 0 0x100>;
581 reg = <0 0x10200620 0 0x20>;
586 reg = <0 0x10205000 0 0x1000>;
598 reg = <0 0x10206000 0 0x1000>;
603 reg = <0x040 0x4>;
607 reg = <0x044 0x4>;
611 reg = <0x528 0xc>;
617 reg = <0 0x10209000 0 0x1000>;
623 reg = <0 0x10209100 0 0x24>;
627 mediatek,ibias = <0xa>;
628 mediatek,ibias_up = <0x1c>;
629 #clock-cells = <0>;
630 #phy-cells = <0>;
636 reg = <0 0x10212000 0 0x1000>;
645 reg = <0 0x10215000 0 0x1000>;
648 #clock-cells = <0>;
649 #phy-cells = <0>;
655 reg = <0 0x10216000 0 0x1000>;
658 #clock-cells = <0>;
659 #phy-cells = <0>;
668 reg = <0 0x10221000 0 0x1000>,
669 <0 0x10222000 0 0x2000>,
670 <0 0x10224000 0 0x2000>,
671 <0 0x10226000 0 0x2000>;
678 reg = <0 0x11001000 0 0x1000>;
687 reg = <0 0x11002000 0 0x400>;
697 reg = <0 0x11003000 0 0x400>;
707 reg = <0 0x11004000 0 0x400>;
717 reg = <0 0x11005000 0 0x400>;
726 reg = <0 0x11007000 0 0x70>,
727 <0 0x11000100 0 0x80>;
734 pinctrl-0 = <&i2c0_pins_a>;
736 #size-cells = <0>;
742 reg = <0 0x11008000 0 0x70>,
743 <0 0x11000180 0 0x80>;
750 pinctrl-0 = <&i2c1_pins_a>;
752 #size-cells = <0>;
758 reg = <0 0x11009000 0 0x70>,
759 <0 0x11000200 0 0x80>;
766 pinctrl-0 = <&i2c2_pins_a>;
768 #size-cells = <0>;
775 #size-cells = <0>;
776 reg = <0 0x1100a000 0 0x1000>;
786 #thermal-sensor-cells = <0>;
788 reg = <0 0x1100b000 0 0x1000>;
789 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
801 reg = <0 0x1100d000 0 0xe0>;
809 #size-cells = <0>;
815 reg = <0 0x11010000 0 0x70>,
816 <0 0x11000280 0 0x80>;
823 pinctrl-0 = <&i2c3_pins_a>;
825 #size-cells = <0>;
831 reg = <0 0x11011000 0 0x70>,
832 <0 0x11000300 0 0x80>;
839 pinctrl-0 = <&i2c4_pins_a>;
841 #size-cells = <0>;
848 reg = <0 0x11012000 0 0x1C>;
855 reg = <0 0x11013000 0 0x70>,
856 <0 0x11000080 0 0x80>;
863 pinctrl-0 = <&i2c6_pins_a>;
865 #size-cells = <0>;
871 reg = <0 0x11220000 0 0x1000>;
903 reg = <0 0x11230000 0 0x1000>;
913 reg = <0 0x11240000 0 0x1000>;
923 reg = <0 0x11250000 0 0x1000>;
933 reg = <0 0x11260000 0 0x1000>;
943 reg = <0 0x11271000 0 0x3000>,
944 <0 0x11280700 0 0x0100>;
953 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
962 reg = <0 0x11270000 0 0x1000>;
974 reg = <0 0x11290000 0 0x800>;
981 reg = <0 0x11290800 0 0x100>;
989 reg = <0 0x11290900 0 0x700>;
997 reg = <0 0x11291000 0 0x100>;
1007 reg = <0 0x14000000 0 0x1000>;
1013 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1021 reg = <0 0x14001000 0 0x1000>;
1031 reg = <0 0x14002000 0 0x1000>;
1040 reg = <0 0x14003000 0 0x1000>;
1047 reg = <0 0x14004000 0 0x1000>;
1054 reg = <0 0x14005000 0 0x1000>;
1061 reg = <0 0x14006000 0 0x1000>;
1069 reg = <0 0x14007000 0 0x1000>;
1077 reg = <0 0x14008000 0 0x1000>;
1085 reg = <0 0x1400c000 0 0x1000>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1095 reg = <0 0x1400d000 0 0x1000>;
1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1105 reg = <0 0x1400e000 0 0x1000>;
1110 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1115 reg = <0 0x1400f000 0 0x1000>;
1120 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1125 reg = <0 0x14010000 0 0x1000>;
1130 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1135 reg = <0 0x14011000 0 0x1000>;
1140 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1145 reg = <0 0x14012000 0 0x1000>;
1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1155 reg = <0 0x14013000 0 0x1000>;
1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1164 reg = <0 0x14014000 0 0x1000>;
1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1173 reg = <0 0x14015000 0 0x1000>;
1177 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1182 reg = <0 0x14016000 0 0x1000>;
1186 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1191 reg = <0 0x14017000 0 0x1000>;
1198 reg = <0 0x14018000 0 0x1000>;
1205 reg = <0 0x14019000 0 0x1000>;
1212 reg = <0 0x1401a000 0 0x1000>;
1216 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1221 reg = <0 0x1401b000 0 0x1000>;
1236 reg = <0 0x1401c000 0 0x1000>;
1250 reg = <0 0x1401d000 0 0x1000>;
1268 reg = <0 0x1401e000 0 0x1000>;
1278 reg = <0 0x1401f000 0 0x1000>;
1288 reg = <0 0x14020000 0 0x1000>;
1292 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1299 reg = <0 0x14021000 0 0x1000>;
1309 reg = <0 0x14022000 0 0x1000>;
1318 reg = <0 0x14023000 0 0x1000>;
1320 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1325 reg = <0 0x14025000 0 0x400>;
1333 pinctrl-0 = <&hdmi_pin>;
1336 mediatek,syscon-hdmi = <&mmsys 0x900>;
1343 #size-cells = <0>;
1345 port@0 {
1346 reg = <0>;
1357 reg = <0 0x14027000 0 0x1000>;
1367 reg = <0 0x15000000 0 0x1000>;
1373 reg = <0 0x15001000 0 0x1000>;
1383 reg = <0 0x16000000 0 0x1000>;
1389 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1390 <0 0x16021000 0 0x800>, /* VDEC_LD */
1391 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1392 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1393 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1394 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1395 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1396 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1397 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1398 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1399 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1438 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1443 reg = <0 0x16010000 0 0x1000>;
1453 reg = <0 0x18000000 0 0x1000>;
1459 reg = <0 0x18001000 0 0x1000>;
1469 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1492 reg = <0 0x18004000 0 0x1000>;
1505 reg = <0 0x19000000 0 0x1000>;
1511 reg = <0 0x19001000 0 0x1000>;
1521 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */