Lines Matching +full:0 +full:xfd4a0000
19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x3>;
58 cpu_suspend = <0x84000001>;
59 cpu_off = <0x84000002>;
60 cpu_on = <0x84000003>;
67 reg = <0x0 0xc0001000 0x1000>,
68 <0x0 0xc0002000 0x2000>,
69 <0x0 0xc0004000 0x2000>,
70 <0x0 0xc0006000 0x2000>;
87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
89 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
93 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
98 #clock-cells = <0>;
115 reg = <0x0 0xfd100000 0x1000>;
122 reg = <0x0 0xfd200000 0x1000>;
129 reg = <0x0 0xfe000000 0x1000>;
130 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
137 reg = <0x0 0xfe100000 0x1000>;
145 reg = <0x0 0xfe200000 0x1000>;
153 reg = <0x0 0xfe800000 0x1000>;
160 reg = <0x0 0xfe900000 0x1000>;
167 reg = <0x0 0xc1128000 0x1000>;
177 reg = <0x0 0xfd400000 0x1000>;
186 reg = <0x0 0xfd410000 0x1000>;
195 reg = <0x0 0xfd420000 0x1000>;
204 reg = <0x0 0xfd430000 0x1000>;
212 reg = <0x0 0xfd440000 0x1000>;
221 reg = <0x0 0xfd450000 0x1000>;
230 reg = <0x0 0xfd460000 0x1000>;
239 reg = <0x0 0xfd470000 0x1000>;
248 reg = <0x0 0xfd480000 0x1000>;
257 reg = <0x0 0xfd490000 0x1000>;
266 reg = <0x0 0xfd4a0000 0x1000>;
275 reg = <0x0 0xfd4b0000 0x1000>;
283 reg = <0x0 0xfd4c0000 0x1000>;
292 reg = <0x0 0xfd4d0000 0x1000>;
301 reg = <0x0 0xfd4e0000 0x1000>;
310 reg = <0x0 0xfd4f0000 0x1000>;
319 reg = <0x0 0xfd500000 0x1000>;
328 reg = <0x0 0xfd510000 0x1000>;