Lines Matching +full:0 +full:x30390000
49 #size-cells = <0>;
56 arm,psci-suspend-param = <0x0010033>;
65 A53_0: cpu@0 {
68 reg = <0x0>;
71 i-cache-size = <0x8000>;
74 d-cache-size = <0x8000>;
88 reg = <0x1>;
91 i-cache-size = <0x8000>;
94 d-cache-size = <0x8000>;
106 reg = <0x2>;
109 i-cache-size = <0x8000>;
112 d-cache-size = <0x8000>;
124 reg = <0x3>;
127 i-cache-size = <0x8000>;
130 d-cache-size = <0x8000>;
143 cache-size = <0x80000>;
156 opp-supported-hw = <0x8a0>, <0x7>;
164 opp-supported-hw = <0xa0>, <0x7>;
172 opp-supported-hw = <0x20>, <0x3>;
180 #clock-cells = <0>;
187 #clock-cells = <0>;
194 #clock-cells = <0>;
201 #clock-cells = <0>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
229 #size-cells = <0>;
231 port@0 {
232 reg = <0>;
280 reg = <0 0x92400000 0 0x1000000>;
301 thermal-sensors = <&tmu 0>;
375 soc: soc@0 {
379 ranges = <0x0 0x0 0x0 0x3e000000>;
385 reg = <0x28440000 0x1000>;
401 reg = <0x28540000 0x1000>;
417 reg = <0x28640000 0x1000>;
433 reg = <0x28740000 0x1000>;
449 reg = <0x28c03000 0x1000>;
455 #size-cells = <0>;
457 port@0 {
458 reg = <0>;
494 reg = <0x28c04000 0x1000>;
517 reg = <0x28c06000 0x1000>;
532 reg = <0x30000000 0x400000>;
539 reg = <0x30200000 0x10000>;
547 gpio-ranges = <&iomuxc 0 5 30>;
552 reg = <0x30210000 0x10000>;
560 gpio-ranges = <&iomuxc 0 35 21>;
565 reg = <0x30220000 0x10000>;
573 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
578 reg = <0x30230000 0x10000>;
586 gpio-ranges = <&iomuxc 0 82 32>;
591 reg = <0x30240000 0x10000>;
599 gpio-ranges = <&iomuxc 0 114 30>;
604 reg = <0x30260000 0x10000>;
613 reg = <0x30280000 0x10000>;
621 reg = <0x30290000 0x10000>;
629 reg = <0x302a0000 0x10000>;
637 reg = <0x302d0000 0x10000>;
645 reg = <0x302e0000 0x10000>;
653 reg = <0x302f0000 0x10000>;
661 reg = <0x30330000 0x10000>;
666 reg = <0x30340000 0x10000>;
671 reg = <0x30350000 0x10000>;
683 * Fuse Address = (ADDR * 4) + 0x400
686 * +0x10 in Fusemap Description Table (e.g.
687 * reg = <0x8 0x8> describes fuses 0x420 and
688 * 0x430).
690 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
691 reg = <0x8 0x8>;
694 cpu_speed_grade: speed-grade@10 { /* 0x440 */
695 reg = <0x10 4>;
698 eth_mac1: mac-address@90 { /* 0x640 */
699 reg = <0x90 6>;
702 eth_mac2: mac-address@96 { /* 0x658 */
703 reg = <0x96 6>;
706 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
707 reg = <0x264 0x10>;
713 reg = <0x30360000 0x10000>;
718 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
719 reg = <0x30370000 0x10000>;
722 compatible = "fsl,sec-v4.0-mon-rtc-lp";
724 offset = <0x34>;
732 compatible = "fsl,sec-v4.0-pwrkey";
750 reg = <0x30380000 0x10000>;
768 assigned-clock-rates = <0>, <0>,
776 reg = <0x30390000 0x10000>;
783 reg = <0x303a0000 0x1000>;
791 #size-cells = <0>;
793 pgc_mipi_phy1: power-domain@0 {
794 #power-domain-cells = <0>;
799 #power-domain-cells = <0>;
804 #power-domain-cells = <0>;
809 #power-domain-cells = <0>;
814 #power-domain-cells = <0>;
831 #power-domain-cells = <0>;
844 #power-domain-cells = <0>;
851 #power-domain-cells = <0>;
863 #power-domain-cells = <0>;
869 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
884 #power-domain-cells = <0>;
889 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
899 #power-domain-cells = <0>;
911 #power-domain-cells = <0>;
916 #power-domain-cells = <0>;
921 #power-domain-cells = <0>;
931 #power-domain-cells = <0>;
941 reg = <0x30400000 0x400000>;
948 reg = <0x30660000 0x10000>;
959 reg = <0x30670000 0x10000>;
970 reg = <0x30680000 0x10000>;
981 reg = <0x30690000 0x10000>;
992 reg = <0x306a0000 0x20000>;
1000 reg = <0x306e0000 0x10000>;
1008 reg = <0x306f0000 0x10000>;
1016 reg = <0x30700000 0x10000>;
1025 reg = <0x30800000 0x400000>;
1032 reg = <0x30800000 0x100000>;
1039 #size-cells = <0>;
1041 reg = <0x30820000 0x10000>;
1049 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1056 #size-cells = <0>;
1058 reg = <0x30830000 0x10000>;
1073 #size-cells = <0>;
1075 reg = <0x30840000 0x10000>;
1090 reg = <0x30860000 0x10000>;
1095 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1102 reg = <0x30880000 0x10000>;
1107 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1114 reg = <0x30890000 0x10000>;
1119 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1126 reg = <0x308c0000 0x10000>;
1134 fsl,clk-source = /bits/ 8 <0>;
1135 fsl,stop-mode = <&gpr 0x10 4>;
1141 reg = <0x308d0000 0x10000>;
1149 fsl,clk-source = /bits/ 8 <0>;
1150 fsl,stop-mode = <&gpr 0x10 5>;
1156 compatible = "fsl,sec-v4.0";
1159 reg = <0x30900000 0x40000>;
1160 ranges = <0 0x30900000 0x40000>;
1167 compatible = "fsl,sec-v4.0-job-ring";
1168 reg = <0x1000 0x1000>;
1174 compatible = "fsl,sec-v4.0-job-ring";
1175 reg = <0x2000 0x1000>;
1180 compatible = "fsl,sec-v4.0-job-ring";
1181 reg = <0x3000 0x1000>;
1189 #size-cells = <0>;
1190 reg = <0x30a20000 0x10000>;
1199 #size-cells = <0>;
1200 reg = <0x30a30000 0x10000>;
1209 #size-cells = <0>;
1210 reg = <0x30a40000 0x10000>;
1219 #size-cells = <0>;
1220 reg = <0x30a50000 0x10000>;
1228 reg = <0x30a60000 0x10000>;
1233 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1240 reg = <0x30aa0000 0x10000>;
1248 reg = <0x30e60000 0x10000>;
1258 #size-cells = <0>;
1259 reg = <0x30ad0000 0x10000>;
1268 #size-cells = <0>;
1269 reg = <0x30ae0000 0x10000>;
1277 reg = <0x30b40000 0x10000>;
1291 reg = <0x30b50000 0x10000>;
1305 reg = <0x30b60000 0x10000>;
1319 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1328 #size-cells = <0>;
1334 reg = <0x30bd0000 0x10000>;
1345 reg = <0x30be0000 0x10000>;
1365 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1370 fsl,stop-mode = <&gpr 0x10 3>;
1376 reg = <0x30bf0000 0x10000>;
1391 assigned-clock-rates = <0>, <100000000>, <125000000>;
1394 intf_mode = <&gpr 0x4>;
1401 reg = <0x30c00000 0x400000>;
1408 reg = <0x30c00000 0x100000>;
1415 reg = <0x30c10000 0x10000>;
1416 #sound-dai-cells = <0>;
1423 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1431 reg = <0x30c20000 0x10000>;
1432 #sound-dai-cells = <0>;
1439 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1447 reg = <0x30c30000 0x10000>;
1448 #sound-dai-cells = <0>;
1455 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1463 reg = <0x30c50000 0x10000>;
1464 #sound-dai-cells = <0>;
1471 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1479 reg = <0x30c60000 0x10000>;
1480 #sound-dai-cells = <0>;
1487 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1495 reg = <0x30c80000 0x10000>;
1496 #sound-dai-cells = <0>;
1503 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1511 reg = <0x30c90000 0x10000>;
1515 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1516 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1517 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1518 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1531 reg = <0x30ca0000 0x10000>;
1532 #sound-dai-cells = <0>;
1544 dmas = <&sdma2 24 25 0x80000000>;
1551 reg = <0x30cb0000 0x10000>;
1555 dmas = <&sdma2 26 2 0>;
1562 reg = <0x30cc0000 0x800>,
1563 <0x30cc0800 0x400>,
1564 <0x30cc0c00 0x080>,
1565 <0x30cc0e00 0x080>;
1568 interrupts = /* XCVR IRQ 0 */
1579 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
1581 resets = <&audio_blk_ctrl 0>;
1588 reg = <0x30e00000 0x10000>;
1599 reg = <0x30e10000 0x10000>;
1610 reg = <0x30e20000 0x10000>;
1633 reg = <0x32700000 0x100000>;
1659 reg = <0x32c00000 0x400000>;
1666 reg = <0x32e00000 0x4000>;
1678 #size-cells = <0>;
1680 port@0 {
1681 reg = <0>;
1700 reg = <0x32e10000 0x10000>;
1707 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1712 #size-cells = <0>;
1722 reg = <0x32e20000 0x10000>;
1734 #size-cells = <0>;
1744 reg = <0x32e30000 0x10000>;
1754 reg = <0x32e40000 0x10000>;
1771 #size-cells = <0>;
1773 port@0 {
1774 reg = <0>;
1789 reg = <0x32e50000 0x10000>;
1806 #size-cells = <0>;
1808 port@0 {
1809 reg = <0>;
1824 reg = <0x32e60000 0x400>;
1840 #size-cells = <0>;
1842 port@0 {
1843 reg = <0>;
1861 reg = <0x32e80000 0x10000>;
1879 reg = <0x32e90000 0x10000>;
1898 reg = <0x32ec0000 0x10000>;
1956 <0>, <0>, <500000000>,
1962 reg = <0x5c 0x4>, <0x128 0x4>;
1972 #size-cells = <0>;
1974 port@0 {
1975 reg = <0>;
2001 reg = <0x32f00000 0x10000>;
2006 #phy-cells = <0>;
2012 reg = <0x32f10000 0x24>;
2027 #clock-cells = <0>;
2032 reg = <0x32fc0000 0x1000>;
2053 reg = <0x32fc2000 0x1000>;
2066 reg = <0x32fc4000 0x1000>;
2074 #size-cells = <0>;
2076 port@0 {
2077 reg = <0>;
2094 reg = <0x32fc6000 0x1000>;
2113 reg = <0x32fd8000 0x7eff>;
2115 interrupts = <0>;
2129 #size-cells = <0>;
2131 port@0 {
2132 reg = <0>;
2148 reg = <0x32fdff00 0x100>;
2155 #clock-cells = <0>;
2156 #phy-cells = <0>;
2163 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
2175 bus-range = <0x00 0xff>;
2176 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
2177 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2183 interrupt-map-mask = <0 0 0 0x7>;
2184 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2185 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2186 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2187 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
2189 linux,pci-domain = <0>;
2201 reg = <0x33800000 0x100000>,
2202 <0x18000000 0x8000000>,
2203 <0x33900000 0x100000>,
2204 <0x33b00000 0x100000>;
2230 reg = <0x38000000 0x8000>;
2248 reg = <0x38008000 0x8000>;
2263 reg = <0x38300000 0x10000>;
2274 reg = <0x38310000 0x10000>;
2285 reg = <0x38330000 0x100>;
2305 reg = <0x38500000 0x200000>;
2318 reg = <0x38800000 0x10000>,
2319 <0x38880000 0xc0000>;
2328 reg = <0x3d400000 0x400000>;
2334 reg = <0x3d800000 0x400000>;
2340 reg = <0x381f0040 0x40>;
2346 #phy-cells = <0>;
2352 reg = <0x32f10100 0x8>,
2353 <0x381f0000 0x20>;
2361 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2367 reg = <0x38100000 0x10000>;
2383 reg = <0x382f0040 0x40>;
2389 #phy-cells = <0>;
2395 reg = <0x32f10108 0x8>,
2396 <0x382f0000 0x20>;
2404 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2410 reg = <0x38200000 0x10000>;
2425 reg = <0x3b6e8000 0x88000>;
2433 mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>;