Lines Matching +full:gic +full:- +full:400
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
58 compatible = "arm,cortex-a57";
60 enable-method = "psci";
61 next-level-cache = <&CLUSTER0_L2>;
66 compatible = "arm,cortex-a57";
68 enable-method = "psci";
69 next-level-cache = <&CLUSTER0_L2>;
74 compatible = "arm,cortex-a57";
76 enable-method = "psci";
77 next-level-cache = <&CLUSTER0_L2>;
80 CLUSTER0_L2: l2-cache@0 {
82 cache-level = <2>;
83 cache-unified;
88 compatible = "arm,psci-1.0";
93 compatible = "arm,armv8-timer";
105 compatible = "arm,cortex-a57-pmu";
110 interrupt-affinity = <&A57_0>,
117 compatible = "brcm,iproc-pcie";
119 dma-coherent;
121 #interrupt-cells = <1>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
125 linux,pci-domain = <0>;
127 bus-range = <0x00 0xff>;
129 #address-cells = <3>;
130 #size-cells = <2>;
134 brcm,pcie-ob;
135 brcm,pcie-ob-oarr-size;
136 brcm,pcie-ob-axi-offset = <0x00000000>;
141 phy-names = "pcie-phy";
143 msi-parent = <&v2m0>;
147 compatible = "brcm,iproc-pcie";
149 dma-coherent;
151 #interrupt-cells = <1>;
152 interrupt-map-mask = <0 0 0 0>;
153 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
155 linux,pci-domain = <4>;
157 bus-range = <0x00 0xff>;
159 #address-cells = <3>;
160 #size-cells = <2>;
164 brcm,pcie-ob;
165 brcm,pcie-ob-oarr-size;
166 brcm,pcie-ob-axi-offset = <0x30000000>;
171 phy-names = "pcie-phy";
173 msi-parent = <&v2m0>;
177 compatible = "brcm,iproc-pcie-paxc";
179 dma-coherent;
180 linux,pci-domain = <8>;
182 bus-range = <0x0 0x1>;
184 #address-cells = <3>;
185 #size-cells = <2>;
191 msi-parent = <&v2m0>;
195 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <1>;
200 #include "ns2-clock.dtsi"
203 compatible = "brcm,ns2-amac";
207 reg-names = "amac_base", "idm_base", "nicpm_base";
209 dma-coherent;
210 phy-handle = <&gphy0>;
211 phy-mode = "rgmii";
215 pdc0: iproc-pdc0@612c0000 {
216 compatible = "brcm,iproc-pdc-mbox";
219 #mbox-cells = <1>;
220 dma-coherent;
221 brcm,rx-status-len = <32>;
222 brcm,use-bcm-hdr;
226 compatible = "brcm,spum-crypto";
231 pdc1: iproc-pdc1@612e0000 {
232 compatible = "brcm,iproc-pdc-mbox";
235 #mbox-cells = <1>;
236 dma-coherent;
237 brcm,rx-status-len = <32>;
238 brcm,use-bcm-hdr;
242 compatible = "brcm,spum-crypto";
247 pdc2: iproc-pdc2@61300000 {
248 compatible = "brcm,iproc-pdc-mbox";
251 #mbox-cells = <1>;
252 dma-coherent;
253 brcm,rx-status-len = <32>;
254 brcm,use-bcm-hdr;
258 compatible = "brcm,spum-crypto";
263 pdc3: iproc-pdc3@61320000 {
264 compatible = "brcm,iproc-pdc-mbox";
267 #mbox-cells = <1>;
268 dma-coherent;
269 brcm,rx-status-len = <32>;
270 brcm,use-bcm-hdr;
274 compatible = "brcm,spum-crypto";
279 dma0: dma-controller@61360000 {
291 #dma-cells = <1>;
293 clock-names = "apb_pclk";
297 compatible = "arm,mmu-500";
299 #global-interrupts = <2>;
334 #iommu-cells = <1>;
338 compatible = "brcm,ns2-pinmux";
345 compatible = "brcm,iproc-gpio";
349 #gpio-cells = <2>;
350 gpio-controller;
353 gic: interrupt-controller@65210000 {
354 compatible = "arm,gic-400";
355 #interrupt-cells = <3>;
356 interrupt-controller;
364 #address-cells = <1>;
365 #size-cells = <1>;
369 compatible = "arm,gic-v2m-frame";
370 msi-controller;
372 arm,msi-base-spi = <72>;
373 arm,msi-num-spis = <16>;
377 compatible = "arm,gic-v2m-frame";
378 msi-controller;
380 arm,msi-base-spi = <88>;
381 arm,msi-num-spis = <16>;
385 compatible = "arm,gic-v2m-frame";
386 msi-controller;
388 arm,msi-base-spi = <104>;
389 arm,msi-num-spis = <16>;
393 compatible = "arm,gic-v2m-frame";
394 msi-controller;
396 arm,msi-base-spi = <120>;
397 arm,msi-num-spis = <16>;
401 compatible = "arm,gic-v2m-frame";
402 msi-controller;
404 arm,msi-base-spi = <136>;
405 arm,msi-num-spis = <16>;
409 compatible = "arm,gic-v2m-frame";
410 msi-controller;
412 arm,msi-base-spi = <152>;
413 arm,msi-num-spis = <16>;
417 compatible = "arm,gic-v2m-frame";
418 msi-controller;
420 arm,msi-base-spi = <168>;
421 arm,msi-num-spis = <16>;
425 compatible = "arm,gic-v2m-frame";
426 msi-controller;
428 arm,msi-base-spi = <184>;
429 arm,msi-num-spis = <16>;
434 compatible = "arm,cci-400";
435 #address-cells = <1>;
436 #size-cells = <1>;
441 compatible = "arm,cci-400-pmu,r1",
442 "arm,cci-400-pmu";
454 #phy-cells = <0>;
455 compatible = "brcm,ns2-drd-phy";
460 reg-names = "icfg", "rst-ctrl",
461 "crmu-ctrl", "usb2-strap";
462 id-gpios = <&gpio_g 30 0>;
463 vbus-gpios = <&gpio_g 31 0>;
468 compatible = "brcm,iproc-pwm";
471 #pwm-cells = <3>;
475 mdio_mux_iproc: mdio-mux@66020000 {
476 compatible = "brcm,mdio-mux-iproc";
478 #address-cells = <1>;
479 #size-cells = <0>;
483 #address-cells = <1>;
484 #size-cells = <0>;
486 pci_phy0: pci-phy@0 {
487 compatible = "brcm,ns2-pcie-phy";
489 #phy-cells = <0>;
496 #address-cells = <1>;
497 #size-cells = <0>;
499 pci_phy1: pci-phy@0 {
500 compatible = "brcm,ns2-pcie-phy";
502 #phy-cells = <0>;
509 #address-cells = <1>;
510 #size-cells = <0>;
521 clock-names = "timer1", "timer2", "apb_pclk";
531 clock-names = "timer1", "timer2", "apb_pclk";
541 clock-names = "timer1", "timer2", "apb_pclk";
551 clock-names = "timer1", "timer2", "apb_pclk";
555 compatible = "brcm,iproc-i2c";
557 #address-cells = <1>;
558 #size-cells = <0>;
560 clock-frequency = <100000>;
569 clock-names = "wdog_clk", "apb_pclk";
573 compatible = "brcm,iproc-gpio";
576 #gpio-cells = <2>;
577 gpio-controller;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
584 compatible = "brcm,iproc-i2c";
586 #address-cells = <1>;
587 #size-cells = <0>;
589 clock-frequency = <100000>;
594 compatible = "snps,dw-apb-uart";
598 reg-shift = <2>;
599 reg-io-width = <4>;
604 compatible = "snps,dw-apb-uart";
608 reg-shift = <2>;
609 reg-io-width = <4>;
614 compatible = "snps,dw-apb-uart";
618 reg-shift = <2>;
619 reg-io-width = <4>;
624 compatible = "snps,dw-apb-uart";
627 reg-shift = <2>;
628 reg-io-width = <4>;
638 clock-names = "sspclk", "apb_pclk";
639 #address-cells = <1>;
640 #size-cells = <0>;
649 clock-names = "sspclk", "apb_pclk";
650 #address-cells = <1>;
651 #size-cells = <0>;
656 compatible = "brcm,iproc-rng200";
661 compatible = "brcm,iproc-ns2-sata-phy";
664 reg-names = "phy", "phy-ctrl";
665 #address-cells = <1>;
666 #size-cells = <0>;
668 sata_phy0: sata-phy@0 {
670 #phy-cells = <0>;
674 sata_phy1: sata-phy@1 {
676 #phy-cells = <0>;
682 compatible = "brcm,iproc-ahci", "generic-ahci";
684 dma-coherent;
685 reg-names = "ahci";
687 #address-cells = <1>;
688 #size-cells = <0>;
691 sata0: sata-port@0 {
694 phy-names = "sata-phy";
697 sata1: sata-port@1 {
700 phy-names = "sata-phy";
705 compatible = "brcm,sdhci-iproc-cygnus";
708 dma-coherent;
709 bus-width = <8>;
715 compatible = "brcm,sdhci-iproc-cygnus";
718 dma-coherent;
719 bus-width = <8>;
725 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
729 reg-names = "nand", "iproc-idm", "iproc-ext";
732 #address-cells = <1>;
733 #size-cells = <0>;
735 brcm,nand-has-wp;
739 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
744 reg-names = "mspi", "bspi", "intr_regs",
747 interrupt-names = "spi_l1_intr";
749 clock-names = "iprocmed";
750 num-cs = <2>;
751 #address-cells = <1>;
752 #size-cells = <0>;