Lines Matching +full:master +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
14 interrupt-parent = <&gic500>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
26 enable-method = "spin-table";
27 cpu-release-addr = <0x0 0x3c0013a0>;
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <128>;
31 i-cache-size = <0x8000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 next-level-cache = <&l2>;
39 compatible = "arm,cortex-a53";
41 enable-method = "spin-table";
42 cpu-release-addr = <0x0 0x3c0013a0>;
43 d-cache-size = <0x8000>;
44 d-cache-line-size = <64>;
45 d-cache-sets = <128>;
46 i-cache-size = <0x8000>;
47 i-cache-line-size = <64>;
48 i-cache-sets = <256>;
49 next-level-cache = <&l2>;
54 compatible = "arm,cortex-a53";
56 enable-method = "spin-table";
57 cpu-release-addr = <0x0 0x3c0013a0>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <64>;
60 d-cache-sets = <128>;
61 i-cache-size = <0x8000>;
62 i-cache-line-size = <64>;
63 i-cache-sets = <256>;
64 next-level-cache = <&l2>;
69 compatible = "arm,cortex-a53";
71 enable-method = "spin-table";
72 cpu-release-addr = <0x0 0x3c0013a0>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <128>;
76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <256>;
79 next-level-cache = <&l2>;
82 l2: l2-cache0 {
84 cache-size = <0x100000>;
85 cache-unified;
86 cache-line-size = <64>;
87 cache-sets = <1024>;
88 cache-level = <2>;
93 clk_xin: clock-200000000 {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <200000000>;
97 clock-output-names = "clk_xin";
100 refclk: clock-125000000 {
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <125000000>;
108 compatible = "simple-bus";
110 #address-cells = <2>;
111 #size-cells = <2>;
112 interrupt-parent = <&gic500>;
114 gic500: interrupt-controller@80300000 {
115 compatible = "arm,gic-v3";
119 #interrupt-cells = <3>;
120 #address-cells = <2>;
121 #size-cells = <2>;
122 interrupt-controller;
123 #redistributor-regions = <1>;
127 /* GPIO Controller banks 0 - 7 */
128 gpio0: gpio-controller@80500000 {
129 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
132 interrupt-parent = <&gic500>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
141 gpio1: gpio-controller@80580000 {
142 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
145 interrupt-parent = <&gic500>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
154 gpio2: gpio-controller@80600000 {
155 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
158 interrupt-parent = <&gic500>;
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
167 gpio3: gpio-controller@80680000 {
168 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
171 interrupt-parent = <&gic500>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
180 gpio4: gpio-controller@80700000 {
181 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
184 interrupt-parent = <&gic500>;
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
193 gpio5: gpio-controller@80780000 {
194 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
197 interrupt-parent = <&gic500>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
206 gpio6: gpio-controller@80800000 {
207 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
210 interrupt-parent = <&gic500>;
212 gpio-controller;
213 #gpio-cells = <2>;
214 interrupt-controller;
215 #interrupt-cells = <2>;
219 gpio7: gpio-controller@80880000 {
220 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
223 interrupt-parent = <&gic500>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
232 /* I3C Controller 0 - 16 */
234 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
237 clock-names = "pclk", "sysclk";
238 interrupt-parent = <&gic500>;
240 i2c-scl-hz = <100000>;
241 i3c-scl-hz = <400000>;
242 #address-cells = <3>;
243 #size-cells = <0>;
248 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
251 clock-names = "pclk", "sysclk";
252 interrupt-parent = <&gic500>;
254 i2c-scl-hz = <100000>;
255 i3c-scl-hz = <400000>;
256 #address-cells = <3>;
257 #size-cells = <0>;
262 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
265 clock-names = "pclk", "sysclk";
266 interrupt-parent = <&gic500>;
268 i2c-scl-hz = <100000>;
269 i3c-scl-hz = <400000>;
270 #address-cells = <3>;
271 #size-cells = <0>;
276 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
279 clock-names = "pclk", "sysclk";
280 interrupt-parent = <&gic500>;
282 i2c-scl-hz = <100000>;
283 i3c-scl-hz = <400000>;
284 #address-cells = <3>;
285 #size-cells = <0>;
290 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
293 clock-names = "pclk", "sysclk";
294 interrupt-parent = <&gic500>;
296 i2c-scl-hz = <100000>;
297 i3c-scl-hz = <400000>;
298 #address-cells = <3>;
299 #size-cells = <0>;
304 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
307 clock-names = "pclk", "sysclk";
308 interrupt-parent = <&gic500>;
310 i2c-scl-hz = <100000>;
311 i3c-scl-hz = <400000>;
312 #address-cells = <3>;
313 #size-cells = <0>;
318 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
321 clock-names = "pclk", "sysclk";
322 interrupt-parent = <&gic500>;
324 i2c-scl-hz = <100000>;
325 i3c-scl-hz = <400000>;
326 #address-cells = <3>;
327 #size-cells = <0>;
332 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
335 clock-names = "pclk", "sysclk";
336 interrupt-parent = <&gic500>;
338 i2c-scl-hz = <100000>;
339 i3c-scl-hz = <400000>;
340 #address-cells = <3>;
341 #size-cells = <0>;
346 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
349 clock-names = "pclk", "sysclk";
350 interrupt-parent = <&gic500>;
352 i2c-scl-hz = <100000>;
353 i3c-scl-hz = <400000>;
354 #address-cells = <3>;
355 #size-cells = <0>;
360 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
363 clock-names = "pclk", "sysclk";
364 interrupt-parent = <&gic500>;
366 i2c-scl-hz = <100000>;
367 i3c-scl-hz = <400000>;
368 #address-cells = <3>;
369 #size-cells = <0>;
374 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
377 clock-names = "pclk", "sysclk";
378 interrupt-parent = <&gic500>;
380 i2c-scl-hz = <100000>;
381 i3c-scl-hz = <400000>;
382 #address-cells = <3>;
383 #size-cells = <0>;
388 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
391 clock-names = "pclk", "sysclk";
392 interrupt-parent = <&gic500>;
394 i2c-scl-hz = <100000>;
395 i3c-scl-hz = <400000>;
396 #address-cells = <3>;
397 #size-cells = <0>;
402 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
405 clock-names = "pclk", "sysclk";
406 interrupt-parent = <&gic500>;
408 i2c-scl-hz = <100000>;
409 i3c-scl-hz = <400000>;
410 #address-cells = <3>;
411 #size-cells = <0>;
416 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
419 clock-names = "pclk", "sysclk";
420 interrupt-parent = <&gic500>;
422 i2c-scl-hz = <100000>;
423 i3c-scl-hz = <400000>;
424 #address-cells = <3>;
425 #size-cells = <0>;
430 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
433 clock-names = "pclk", "sysclk";
434 interrupt-parent = <&gic500>;
436 i2c-scl-hz = <100000>;
437 i3c-scl-hz = <400000>;
438 #address-cells = <3>;
439 #size-cells = <0>;
444 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
447 clock-names = "pclk", "sysclk";
448 interrupt-parent = <&gic500>;
450 i2c-scl-hz = <100000>;
451 i3c-scl-hz = <400000>;
452 #address-cells = <3>;
453 #size-cells = <0>;
458 compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
461 clock-names = "pclk", "sysclk";
462 interrupt-parent = <&gic500>;
464 i2c-scl-hz = <100000>;
465 i3c-scl-hz = <400000>;
466 #address-cells = <3>;
467 #size-cells = <0>;
472 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
474 interrupt-parent = <&gic500>;
476 clock-names = "uart_clk", "pclk";
482 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
484 interrupt-parent = <&gic500>;
486 clock-names = "uart_clk", "pclk";
492 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
494 interrupt-parent = <&gic500>;
496 clock-names = "uart_clk", "pclk";
502 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
504 interrupt-parent = <&gic500>;
506 clock-names = "uart_clk", "pclk";
513 compatible = "arm,armv8-timer";
514 interrupt-parent = <&gic500>;