Lines Matching refs:pp
75 struct pcie_port *pp = pcie_port + i;
77 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
78 "PCIe %d.%d MEM", pp->maj, pp->min);
79 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
80 pp->res.name = pp->mem_space_name;
81 pp->res.flags = IORESOURCE_MEM;
82 pp->res.start = start;
83 pp->res.end = start + size_each - 1;
86 if (request_resource(&iomem_resource, &pp->res))
89 mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
90 MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
91 pp->res.start, resource_size(&pp->res));
92 mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
93 MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
100 struct pcie_port *pp;
106 pp = &pcie_port[nr];
107 sys->private_data = pp;
108 pp->root_bus_nr = sys->busnr;
113 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
114 orion_pcie_setup(pp->base);
120 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
125 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
131 if (bus == pp->root_bus_nr && dev > 1)
141 struct pcie_port *pp = sys->private_data;
145 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
150 spin_lock_irqsave(&pp->conf_lock, flags);
151 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
152 spin_unlock_irqrestore(&pp->conf_lock, flags);
161 struct pcie_port *pp = sys->private_data;
165 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
168 spin_lock_irqsave(&pp->conf_lock, flags);
169 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
170 spin_unlock_irqrestore(&pp->conf_lock, flags);
224 struct pcie_port *pp = sys->private_data;
226 return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
242 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
246 pp->maj = maj;
247 pp->min = min;
248 pp->root_bus_nr = -1;
249 pp->base = base;
250 spin_lock_init(&pp->conf_lock);
251 memset(&pp->res, 0, sizeof(pp->res));