Lines Matching +full:0 +full:x40005800
54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
81 #size-cells = <0>;
83 reg = <0x40000000 0x400>;
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
103 #size-cells = <0>;
105 reg = <0x40000400 0x400>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
125 #size-cells = <0>;
127 reg = <0x40000800 0x400>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
147 #size-cells = <0>;
149 reg = <0x40000C00 0x400>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
169 #size-cells = <0>;
171 reg = <0x40001000 0x400>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
185 #size-cells = <0>;
187 reg = <0x40001400 0x400>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
201 #size-cells = <0>;
203 reg = <0x40001800 0x400>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 reg = <0x40001C00 0x400>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 reg = <0x40002000 0x400>;
238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
251 #size-cells = <0>;
253 reg = <0x40002400 0x400>;
265 trigger@0 {
267 reg = <0>;
284 reg = <0x40002800 0x400>;
290 st,syscfg = <&pwrcfg 0x00 0x100>;
296 #size-cells = <0>;
298 reg = <0x40003800 0x400>;
300 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
306 #size-cells = <0>;
308 reg = <0x40003c00 0x400>;
310 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
316 reg = <0x40004400 0x400>;
324 reg = <0x40004800 0x400>;
332 reg = <0x40004c00 0x400>;
340 reg = <0x40005000 0x400>;
348 reg = <0x40005400 0x400>;
354 #size-cells = <0>;
360 reg = <0x40005800 0x400>;
366 #size-cells = <0>;
372 reg = <0x40005c00 0x400>;
378 #size-cells = <0>;
384 reg = <0x40006000 0x400>;
390 #size-cells = <0>;
396 reg = <0x40006400 0x200>;
400 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
408 reg = <0x40006600 0x200>;
409 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
414 reg = <0x40006800 0x200>;
418 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
426 reg = <0x40006C00 0x400>;
428 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
435 reg = <0x40007800 0x400>;
443 reg = <0x40007c00 0x400>;
451 #size-cells = <0>;
453 reg = <0x40010000 0x400>;
454 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
464 timer@0 {
466 reg = <0>;
473 #size-cells = <0>;
475 reg = <0x40010400 0x400>;
476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
495 reg = <0x40011000 0x400>;
503 reg = <0x40011400 0x400>;
511 arm,primecell-periphid = <0x00880180>;
512 reg = <0x40011c00 0x400>;
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
522 arm,primecell-periphid = <0x00880180>;
523 reg = <0x40012c00 0x400>;
524 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
533 #size-cells = <0>;
535 reg = <0x40013000 0x400>;
537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
543 #size-cells = <0>;
545 reg = <0x40013400 0x400>;
547 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
553 reg = <0x40013800 0x400>;
554 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
561 reg = <0x40013C00 0x400>;
567 #size-cells = <0>;
569 reg = <0x40014000 0x400>;
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
589 reg = <0x40014400 0x400>;
590 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
603 reg = <0x40014800 0x400>;
604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
617 #size-cells = <0>;
619 reg = <0x40015000 0x400>;
621 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
627 #size-cells = <0>;
629 reg = <0x40015400 0x400>;
631 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
637 reg = <0x40016800 0x200>;
647 reg = <0x40007000 0x400>;
652 reg = <0x40023000 0x400>;
653 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
661 reg = <0x40023800 0x400>;
670 reg = <0x40026000 0x400>;
679 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
686 reg = <0x40026400 0x400>;
695 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
703 reg = <0x40040000 0x40000>;
705 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
715 reg = <0x50000000 0x40000>;
717 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
725 clocks = <&rcc 1 0>;