dts/qcom/qcom-ipq4019.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 	#address-cells = <1>;
14 	#size-cells = <1>;
18 	interrupt-parent = <&intc>;
20 	reserved-memory {
21 		#address-cells = <0x1>;
22 		#size-cells = <0x1>;
27 			no-map;
32 			no-map;
44 		#address-cells = <1>;
45 		#size-cells = <0>;
48 			compatible = "arm,cortex-a7";
49 			enable-method = "qcom,kpss-acc-v2";
50 			next-level-cache = <&l2>;
55 			clock-frequency = <0>;
56 			operating-points-v2 = <&cpu0_opp_table>;
61 			compatible = "arm,cortex-a7";
62 			enable-method = "qcom,kpss-acc-v2";
63 			next-level-cache = <&l2>;
68 			clock-frequency = <0>;
69 			operating-points-v2 = <&cpu0_opp_table>;
74 			compatible = "arm,cortex-a7";
75 			enable-method = "qcom,kpss-acc-v2";
76 			next-level-cache = <&l2>;
81 			clock-frequency = <0>;
82 			operating-points-v2 = <&cpu0_opp_table>;
87 			compatible = "arm,cortex-a7";
88 			enable-method = "qcom,kpss-acc-v2";
89 			next-level-cache = <&l2>;
94 			clock-frequency = <0>;
95 			operating-points-v2 = <&cpu0_opp_table>;
98 		l2: l2-cache {
100 			cache-level = <2>;
101 			cache-unified;
106 	cpu0_opp_table: opp-table {
107 		compatible = "operating-points-v2";
108 		opp-shared;
110 		opp-48000000 {
111 			opp-hz = /bits/ 64 <48000000>;
112 			clock-latency-ns = <256000>;
114 		opp-200000000 {
115 			opp-hz = /bits/ 64 <200000000>;
116 			clock-latency-ns = <256000>;
118 		opp-500000000 {
119 			opp-hz = /bits/ 64 <500000000>;
120 			clock-latency-ns = <256000>;
122 		opp-716000000 {
123 			opp-hz = /bits/ 64 <716000000>;
124 			clock-latency-ns = <256000>;
134 		compatible = "arm,cortex-a7-pmu";
141 			compatible = "fixed-clock";
142 			clock-frequency = <32000>;
143 			#clock-cells = <0>;
147 			compatible = "fixed-clock";
148 			clock-frequency = <48000000>;
149 			#clock-cells = <0>;
155 			compatible = "qcom,scm-ipq4019", "qcom,scm";
160 		compatible = "arm,armv7-timer";
165 		clock-frequency = <48000000>;
166 		always-on;
170 		#address-cells = <1>;
171 		#size-cells = <1>;
173 		compatible = "simple-bus";
175 		intc: interrupt-controller@b000000 {
176 			compatible = "qcom,msm-qgic2";
177 			interrupt-controller;
178 			#interrupt-cells = <3>;
183 		gcc: clock-controller@1800000 {
184 			compatible = "qcom,gcc-ipq4019";
185 			#clock-cells = <1>;
186 			#reset-cells = <1>;
189 			clock-names = "xo", "sleep_clk";
196 			clock-names = "core";
201 			compatible = "qcom,ipq4019-pinctrl";
203 			gpio-controller;
204 			gpio-ranges = <&tlmm 0 0 100>;
205 			#gpio-cells = <2>;
206 			interrupt-controller;
207 			#interrupt-cells = <2>;
212 			compatible = "qcom,vqmmc-ipq4019-regulator";
214 			regulator-name = "vqmmc";
215 			regulator-min-microvolt = <1500000>;
216 			regulator-max-microvolt = <3000000>;
217 			regulator-always-on;
222 			compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4";
224 			reg-names = "hc", "core";
226 			interrupt-names = "hc_irq", "pwr_irq";
227 			bus-width = <8>;
231 			clock-names = "iface",
237 		blsp_dma: dma-controller@7884000 {
238 			compatible = "qcom,bam-v1.7.0";
242 			clock-names = "bam_clk";
243 			#dma-cells = <1>;
249 			compatible = "qcom,spi-qup-v2.2.1";
254 			clock-names = "core", "iface";
255 			#address-cells = <1>;
256 			#size-cells = <0>;
258 			dma-names = "tx", "rx";
263 			compatible = "qcom,spi-qup-v2.2.1";
268 			clock-names = "core", "iface";
269 			#address-cells = <1>;
270 			#size-cells = <0>;
272 			dma-names = "tx", "rx";
277 			compatible = "qcom,i2c-qup-v2.2.1";
282 			clock-names = "core", "iface";
283 			#address-cells = <1>;
284 			#size-cells = <0>;
286 			dma-names = "tx", "rx";
291 			compatible = "qcom,i2c-qup-v2.2.1";
296 			clock-names = "core", "iface";
297 			#address-cells = <1>;
298 			#size-cells = <0>;
300 			dma-names = "tx", "rx";
304 		cryptobam: dma-controller@8e04000 {
305 			compatible = "qcom,bam-v1.7.0";
309 			clock-names = "bam_clk";
310 			#dma-cells = <1>;
312 			qcom,controlled-remotely;
317 			compatible = "qcom,crypto-v5.1";
322 			clock-names = "iface", "bus", "core";
324 			dma-names = "rx", "tx";
328 		acc0: power-manager@b088000 {
329 			compatible = "qcom,kpss-acc-v2";
333 		acc1: power-manager@b098000 {
334 			compatible = "qcom,kpss-acc-v2";
338 		acc2: power-manager@b0a8000 {
339 			compatible = "qcom,kpss-acc-v2";
343 		acc3: power-manager@b0b8000 {
344 			compatible = "qcom,kpss-acc-v2";
348 		saw0: power-manager@b089000 {
349 			compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
353 		saw1: power-manager@b099000 {
354 			compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
358 		saw2: power-manager@b0a9000 {
359 			compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
363 		saw3: power-manager@b0b9000 {
364 			compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
368 		saw_l2: power-manager@b012000 {
369 			compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
374 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
380 			clock-names = "core", "iface";
382 			dma-names = "tx", "rx";
386 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
392 			clock-names = "core", "iface";
394 			dma-names = "tx", "rx";
398 			compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
401 			timeout-sec = <10>;
411 			compatible = "qcom,pcie-ipq4019";
416 			reg-names = "dbi", "elbi", "parf", "config";
418 			linux,pci-domain = <0>;
419 			bus-range = <0x00 0xff>;
420 			num-lanes = <1>;
421 			#address-cells = <3>;
422 			#size-cells = <2>;
428 			interrupt-names = "msi";
429 			#interrupt-cells = <1>;
430 			interrupt-map-mask = <0 0 0 0x7>;
431 			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
438 			clock-names = "aux",
454 			reset-names = "axi_m",
472 				bus-range = <0x01 0xff>;
474 				#address-cells = <3>;
475 				#size-cells = <2>;
480 		qpic_bam: dma-controller@7984000 {
481 			compatible = "qcom,bam-v1.7.0";
485 			clock-names = "bam_clk";
486 			#dma-cells = <1>;
491 		nand: nand-controller@79b0000 {
492 			compatible = "qcom,ipq4019-nand";
494 			#address-cells = <1>;
495 			#size-cells = <0>;
498 			clock-names = "core", "aon";
503 			dma-names = "tx", "rx", "cmd";
509 				nand-ecc-strength = <4>;
510 				nand-ecc-step-size = <512>;
511 				nand-bus-width = <8>;
516 			compatible = "qcom,ipq4019-wifi";
524 			reset-names = "wifi_cpu_init", "wifi_radio_srif",
530 			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
549 			interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
558 			compatible = "qcom,ipq4019-wifi";
566 			reset-names = "wifi_cpu_init", "wifi_radio_srif",
572 			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
591 			interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
600 			#address-cells = <1>;
601 			#size-cells = <0>;
602 			compatible = "qcom,ipq4019-mdio";
606 			ethernet-phy-package@0 {
607 				#address-cells = <1>;
608 				#size-cells = <0>;
609 				compatible = "qcom,qca8075-package";
612 				qcom,tx-drive-strength-milliwatt = <300>;
614 				ethphy0: ethernet-phy@0 {
618 				ethphy1: ethernet-phy@1 {
622 				ethphy2: ethernet-phy@2 {
626 				ethphy3: ethernet-phy@3 {
630 				ethphy4: ethernet-phy@4 {
636 		usb3_ss_phy: usb-phy@9a000 {
637 			compatible = "qcom,usb-ss-ipq4019-phy";
638 			#phy-cells = <0>;
640 			reg-names = "phy_base";
642 			reset-names = "por_rst";
646 		usb3_hs_phy: usb-phy@a6000 {
647 			compatible = "qcom,usb-hs-ipq4019-phy";
648 			#phy-cells = <0>;
650 			reg-names = "phy_base";
652 			reset-names = "por_rst", "srif_rst";
657 			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
659 			#address-cells = <1>;
660 			#size-cells = <1>;
664 			clock-names = "core", "sleep", "mock_utmi";
673 				phy-names = "usb2-phy", "usb3-phy";
678 		usb2_hs_phy: usb-phy@a8000 {
679 			compatible = "qcom,usb-hs-ipq4019-phy";
680 			#phy-cells = <0>;
682 			reg-names = "phy_base";
684 			reset-names = "por_rst", "srif_rst";
689 			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
691 			#address-cells = <1>;
692 			#size-cells = <1>;
696 			clock-names = "core", "sleep", "mock_utmi";
705 				phy-names = "usb2-phy";