Lines Matching +full:0 +full:x02008000
25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
174 coefficients = <1132 0>;
199 #clock-cells = <0>;
205 #clock-cells = <0>;
211 #clock-cells = <0>;
227 #size-cells = <0>;
232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
234 apps_smsm: apps@0 {
235 reg = <0>;
297 #size-cells = <0>;
299 port@0 {
300 reg = <0>;
323 reg = <0x800000 0x4000>;
326 gpio-ranges = <&tlmm_pinmux 0 0 90>;
333 pinctrl-0 = <&ps_hold_default_state>;
338 reg = <0x01200600 0x100>;
346 reg = <0x02000000 0x1000>,
347 <0x02002000 0x1000>;
356 reg = <0x0200a000 0x100>;
360 cpu-offset = <0x80000>;
365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
369 #clock-cells = <0>;
374 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
378 #clock-cells = <0>;
383 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
387 #clock-cells = <0>;
392 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
396 #clock-cells = <0>;
401 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
411 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
431 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
441 reg = <0x12100000 0x10000>;
448 reg = <0x12440000 0x100>;
459 reg = <0x12450000 0x100>,
460 <0x12400000 0x03>;
469 pinctrl-0 = <&i2c1_default_state>;
472 reg = <0x12460000 0x1000>;
477 #size-cells = <0>;
487 reg = <0x12480000 0x100>;
498 reg = <0x124a0000 0x1000>;
499 pinctrl-0 = <&i2c2_default_state>;
506 #size-cells = <0>;
515 reg = <0x16200000 0x100>;
523 pinctrl-0 = <&i2c3_default_state>;
526 reg = <0x16280000 0x1000>;
532 #size-cells = <0>;
541 reg = <0x16300000 0x03>;
550 reg = <0x16340000 0x100>,
551 <0x16300000 0x3>;
553 pinctrl-0 = <&gsbi4_uart_pin_a>;
562 pinctrl-0 = <&i2c4_default_state>;
565 reg = <0x16380000 0x1000>;
578 reg = <0x1a200000 0x03>;
587 reg = <0x1a240000 0x100>,
588 <0x1a200000 0x03>;
597 reg = <0x1a280000 0x1000>;
599 pinctrl-0 = <&spi5_default_state>;
606 #size-cells = <0>;
614 reg = <0x16500000 0x03>;
623 reg = <0x16540000 0x100>,
624 <0x16500000 0x03>;
633 pinctrl-0 = <&i2c6_default_state>;
636 reg = <0x16580000 0x1000>;
649 reg = <0x16600000 0x100>;
659 reg = <0x16640000 0x1000>,
660 <0x16600000 0x1000>;
669 pinctrl-0 = <&i2c7_default_state>;
672 reg = <0x16680000 0x1000>;
683 reg = <0x1a500000 0x200>;
690 reg = <0x00c00000 0x1000>;
696 reg = <0x00500000 0x1000>;
702 reg = <0x00700000 0x1000>;
707 reg = <0x404 0x10>;
710 reg = <0x414 0x10>;
716 reg = <0x00900000 0x4000>;
739 reg = <0x28000000 0x1000>;
744 <0>,
745 <0>, <0>,
746 <0>, <0>,
747 <0>;
760 reg = <0x4000000 0x1000>;
768 <&dsi0_phy 0>,
770 <&dsi1_phy 0>,
786 reg = <0x2011000 0x1000>;
789 #clock-cells = <0>;
794 reg = <0x108000 0x1000>;
795 qcom,ipc = <&l2cc 0x8 2>;
812 reg = <0x12500000 0x200>,
813 <0x12500200 0x200>;
822 ahb-burst-config = <0>;
834 resets = <&usb1 0>;
836 #phy-cells = <0>;
843 reg = <0x12520000 0x200>,
844 <0x12520200 0x200>;
853 ahb-burst-config = <0>;
863 #phy-cells = <0>;
866 resets = <&usb3 0>;
874 reg = <0x12530000 0x200>,
875 <0x12530200 0x200>;
884 ahb-burst-config = <0>;
894 #phy-cells = <0>;
897 resets = <&usb4 0>;
906 reg = <0x1b400000 0x200>;
909 #phy-cells = <0>;
915 reg = <0x29000000 0x180>;
935 ports-implemented = <0x1>;
940 arm,primecell-periphid = <0x00051180>;
942 reg = <0x12180000 0x2000>;
957 reg = <0x12182000 0x8000>;
962 qcom,ee = <0>;
967 arm,primecell-periphid = <0x00051180>;
969 reg = <0x121c0000 0x2000>;
980 pinctrl-0 = <&sdc4_default_state>;
985 reg = <0x121c2000 0x8000>;
990 qcom,ee = <0>;
997 pinctrl-0 = <&sdcc1_default_state>;
998 arm,primecell-periphid = <0x00051180>;
999 reg = <0x12400000 0x2000>;
1014 reg = <0x12402000 0x8000>;
1019 qcom,ee = <0>;
1024 reg = <0x1a400000 0x100>;
1029 reg = <0x04300000 0x20000>;
1044 iommus = <&gfx3d 0
1076 &gfx3d1 0
1126 reg = <0x5700000 0x70>;
1133 #size-cells = <0>;
1135 reg = <0x04700000 0x200>;
1153 assigned-clock-parents = <&dsi0_phy 0>,
1154 <&dsi0_phy 0>,
1163 #size-cells = <0>;
1165 port@0 {
1166 reg = <0>;
1183 #phy-cells = <0>;
1185 reg = <0x04700200 0x100>,
1186 <0x04700300 0x200>,
1187 <0x04700500 0x5c>;
1198 reg = <0x05800000 0x200>;
1220 assigned-clock-parents = <&dsi1_phy 0>,
1221 <&dsi1_phy 0>,
1229 #size-cells = <0>;
1235 #size-cells = <0>;
1237 port@0 {
1238 reg = <0>;
1254 reg = <0x05800200 0x100>,
1255 <0x05800300 0x200>,
1256 <0x05800500 0x5c>;
1265 #phy-cells = <0>;
1279 reg = <0x07500000 0x100000>;
1295 reg = <0x07600000 0x100000>;
1311 reg = <0x07c00000 0x100000>;
1327 reg = <0x07d00000 0x100000>;
1336 reg = <0x1b500000 0x1000>,
1337 <0x1b502000 0x80>,
1338 <0x1b600000 0x100>,
1339 <0x0ff00000 0x100000>;
1342 linux,pci-domain = <0>;
1343 bus-range = <0x00 0xff>;
1347 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
1348 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
1352 interrupt-map-mask = <0 0 0 0x7>;
1353 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1354 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1355 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1356 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1369 pcie@0 {
1371 reg = <0x0 0x0 0x0 0x0 0x0>;
1372 bus-range = <0x01 0xff>;
1383 pinctrl-0 = <&hdmi_pinctrl>;
1384 reg = <0x04a00000 0x2f0>;
1400 #size-cells = <0>;
1402 port@0 {
1403 reg = <0>;
1418 reg = <0x4a00400 0x60>,
1419 <0x4a00500 0x100>;
1425 #phy-cells = <0>;
1426 #clock-cells = <0>;
1433 reg = <0x05100000 0xf0000>;
1452 #clock-cells = <0>;
1454 iommus = <&mdp_port0 0
1456 &mdp_port1 0
1461 #size-cells = <0>;
1463 port@0 {
1464 reg = <0>;
1492 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1544 reg = <0x1a01000 0x1000>;
1560 reg = <0x1a03000 0x1000>;
1576 reg = <0x1a04000 0x1000>;
1583 #size-cells = <0>;
1592 port@0 {
1593 reg = <0>;
1629 reg = <0x1a1c000 0x1000>;
1647 reg = <0x1a1d000 0x1000>;
1665 reg = <0x1a1e000 0x1000>;
1683 reg = <0x1a1f000 0x1000>;