Lines Matching +full:0 +full:x30390000
56 #size-cells = <0>;
63 arm,psci-suspend-param = <0x0010000>;
71 cpu0: cpu@0 {
74 reg = <0>;
93 opp-supported-hw = <0xf>, <0xf>;
99 #clock-cells = <0>;
106 #clock-cells = <0>;
115 #phy-cells = <0>;
123 #phy-cells = <0>;
142 #size-cells = <0>;
144 port@0 {
145 reg = <0>;
180 mux-controls = <&mux 0>;
182 #size-cells = <0>;
185 port@0 {
186 reg = <0>;
215 reg = <0x00900000 0x20000>;
216 ranges = <0 0x00900000 0x20000>;
224 reg = <0x30041000 0x1000>;
230 #size-cells = <0>;
232 port@0 {
233 reg = <0>;
254 reg = <0x3007c000 0x1000>;
270 reg = <0x30083000 0x1000>;
276 #size-cells = <0>;
278 port@0 {
279 reg = <0>;
305 reg = <0x30084000 0x1000>;
328 reg = <0x30086000 0x1000>;
343 reg = <0x30087000 0x1000>;
362 reg = <0x31001000 0x1000>,
363 <0x31002000 0x2000>,
364 <0x31004000 0x2000>,
365 <0x31006000 0x2000>;
372 reg = <0x30000000 0x400000>;
377 reg = <0x30200000 0x10000>;
384 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
389 reg = <0x30210000 0x10000>;
396 gpio-ranges = <&iomuxc 0 13 32>;
401 reg = <0x30220000 0x10000>;
408 gpio-ranges = <&iomuxc 0 45 29>;
413 reg = <0x30230000 0x10000>;
420 gpio-ranges = <&iomuxc 0 74 24>;
425 reg = <0x30240000 0x10000>;
432 gpio-ranges = <&iomuxc 0 98 18>;
437 reg = <0x30250000 0x10000>;
444 gpio-ranges = <&iomuxc 0 116 23>;
449 reg = <0x30260000 0x10000>;
456 gpio-ranges = <&iomuxc 0 139 16>;
461 reg = <0x30280000 0x10000>;
468 reg = <0x30290000 0x10000>;
476 reg = <0x302a0000 0x10000>;
484 reg = <0x302b0000 0x10000>;
492 reg = <0x302c0000 0x10000>;
498 reg = <0x302d0000 0x10000>;
507 reg = <0x302e0000 0x10000>;
517 reg = <0x302f0000 0x10000>;
527 reg = <0x30300000 0x10000>;
537 reg = <0x30320000 0x10000>;
545 reg = <0x30330000 0x10000>;
552 reg = <0x30340000 0x10000>;
557 mux-reg-masks = <0x14 0x00000010>;
565 reg = <0x30350000 0x10000>;
569 reg = <0x3c 0x4>;
573 reg = <0x10 0x4>;
580 reg = <0x30360000 0x10000>;
589 anatop-reg-offset = <0x210>;
595 anatop-enable-bit = <0>;
603 anatop-reg-offset = <0x220>;
606 anatop-min-bit-val = <0x14>;
609 anatop-enable-bit = <0>;
620 #thermal-sensor-cells = <0>;
625 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
626 reg = <0x30370000 0x10000>;
629 compatible = "fsl,sec-v4.0-mon-rtc-lp";
631 offset = <0x34>;
641 offset = <0x38>;
642 value = <0x60>;
643 mask = <0x60>;
648 compatible = "fsl,sec-v4.0-pwrkey";
661 reg = <0x30380000 0x10000>;
671 reg = <0x30390000 0x10000>;
678 reg = <0x303a0000 0x10000>;
686 #size-cells = <0>;
688 pgc_mipi_phy: power-domain@0 {
689 #power-domain-cells = <0>;
690 reg = <0>;
695 #power-domain-cells = <0>;
701 #power-domain-cells = <0>;
713 reg = <0x30400000 0x400000>;
718 reg = <0x30610000 0x10000>;
728 reg = <0x30620000 0x10000>;
738 #size-cells = <0>;
740 reg = <0x30630000 0x10000>;
752 reg = <0x30640000 0x10000>;
766 reg = <0x30650000 0x10000>;
780 reg = <0x30660000 0x10000>;
791 reg = <0x30670000 0x10000>;
802 reg = <0x30680000 0x10000>;
813 reg = <0x30690000 0x10000>;
824 reg = <0x30710000 0x10000>;
839 reg = <0x30730000 0x10000>;
849 reg = <0x30750000 0x10000>;
862 #size-cells = <0>;
864 port@0 {
865 reg = <0>;
881 #size-cells = <0>;
882 reg = <0x30760000 0x400>;
889 assigned-clock-rates = <0>, <333000000>;
903 reg = <0x30800000 0x400000>;
910 reg = <0x30800000 0x100000>;
915 #size-cells = <0>;
917 reg = <0x30820000 0x10000>;
923 dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
929 #size-cells = <0>;
931 reg = <0x30830000 0x10000>;
943 #size-cells = <0>;
945 reg = <0x30840000 0x10000>;
958 reg = <0x30860000 0x10000>;
969 reg = <0x30890000 0x10000>;
980 reg = <0x30880000 0x10000>;
989 #sound-dai-cells = <0>;
991 reg = <0x308a0000 0x10000>;
999 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
1004 #sound-dai-cells = <0>;
1006 reg = <0x308b0000 0x10000>;
1014 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
1019 #sound-dai-cells = <0>;
1021 reg = <0x308c0000 0x10000>;
1029 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
1035 compatible = "fsl,sec-v4.0";
1038 reg = <0x30900000 0x40000>;
1039 ranges = <0 0x30900000 0x40000>;
1046 compatible = "fsl,sec-v4.0-job-ring";
1047 reg = <0x1000 0x1000>;
1052 compatible = "fsl,sec-v4.0-job-ring";
1053 reg = <0x2000 0x1000>;
1058 compatible = "fsl,sec-v4.0-job-ring";
1059 reg = <0x3000 0x1000>;
1066 reg = <0x30a00000 0x10000>;
1071 fsl,stop-mode = <&gpr 0x10 1>;
1077 reg = <0x30a10000 0x10000>;
1082 fsl,stop-mode = <&gpr 0x10 2>;
1088 #size-cells = <0>;
1090 reg = <0x30a20000 0x10000>;
1098 #size-cells = <0>;
1100 reg = <0x30a30000 0x10000>;
1108 #size-cells = <0>;
1110 reg = <0x30a40000 0x10000>;
1118 #size-cells = <0>;
1120 reg = <0x30a50000 0x10000>;
1129 reg = <0x30a60000 0x10000>;
1140 reg = <0x30a70000 0x10000>;
1151 reg = <0x30a80000 0x10000>;
1162 reg = <0x30a90000 0x10000>;
1172 reg = <0x30aa0000 0x10000>;
1181 reg = <0x30ab0000 0x10000>;
1191 reg = <0x30b10000 0x200>;
1195 fsl,usbmisc = <&usbmisc1 0>;
1202 reg = <0x30b30000 0x200>;
1206 fsl,usbmisc = <&usbmisc3 0>;
1216 reg = <0x30b10200 0x200>;
1222 reg = <0x30b30200 0x200>;
1227 reg = <0x30b40000 0x10000>;
1241 reg = <0x30b50000 0x10000>;
1255 reg = <0x30b60000 0x10000>;
1269 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1272 #size-cells = <0>;
1282 reg = <0x30bd0000 0x10000>;
1293 reg = <0x30be0000 0x10000>;
1308 fsl,stop-mode = <&gpr 0x10 3>;
1315 reg = <0x33000000 0x2000>;
1328 #size-cells = <0>;
1329 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1336 dmas = <&dma_apbh 0>;