Lines Matching +full:0 +full:x200
27 #size-cells = <0>;
29 cpu0: cpu@0 {
31 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32 KB
36 i-cache-size = <0x8000>; // L1, 32 KB
42 cache-size = <0x40000>; // L2, 256 KB
52 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x100000 0x20000>;
78 reg = <0xe0000800 0x4000>;
79 ranges = <0 0xe0000800 0x4000>;
88 reg = <0xe0004000 0x4000>;
95 reg = <0xe0008000 0x20>;
100 reg = <0xe0014000 0x800>;
115 reg = <0xe0018000 0x200>;
118 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
124 reg = <0xe001d000 0x30>;
126 clocks = <&clk32k 0>;
131 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
133 clocks = <&clk32k 0>;
138 reg = <0xe001d200 0x20>;
139 clocks = <&clk32k 0>;
141 #size-cells = <0>;
149 reg = <0xe001d300 0x30>;
151 clocks = <&clk32k 0>;
156 reg = <0xe001d500 0x4>;
163 reg = <0xe001d700 0x48>;
168 reg = <0xe001d800 0x30>;
175 reg = <0xe0020000 0x8>;
180 reg = <0xe0828000 0x200>, <0x100000 0x7800>;
190 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
196 reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
206 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
212 reg = <0xe0830000 0x200>, <0x100000 0x10000>;
222 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
228 reg = <0xe0834000 0x200>, <0x110000 0x4400>;
238 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
244 reg = <0xe0838000 0x200>, <0x110000 0x8800>;
254 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
260 reg = <0xe1200000 0x1000>;
265 dma-requests = <0>;
271 reg = <0xe1208000 0x400>;
283 reg = <0xe1600000 0x100>;
294 reg = <0xe1604000 0x100>;
304 reg = <0xe1608000 0x100>;
315 reg = <0xe160c000 0x100>;
322 reg = <0xe1610000 0x1000>;
332 reg = <0xe1614000 0x1000>;
342 reg = <0xe1618000 0x2000>;
358 reg = <0xe161c000 0x2000>;
374 reg = <0xe1800000 0x100>;
382 reg = <0xe1804000 0x100>;
390 reg = <0xe1818000 0x500>;
399 reg = <0xe1820000 0x200>;
400 ranges = <0x0 0xe1820000 0x800>;
408 reg = <0x200 0x200>;
423 reg = <0x600 0x200>;
427 #size-cells = <0>;
438 reg = <0xe1824000 0x200>;
439 ranges = <0x0 0xe1824000 0x800>;
447 reg = <0x400 0x200>;
452 #size-cells = <0>;
462 reg = <0x600 0x200>;
466 #size-cells = <0>;
477 reg = <0xe1828000 0x200>;
478 ranges = <0x0 0xe1828000 0x800>;
486 reg = <0x200 0x200>;
502 reg = <0xe182c000 0x200>;
503 ranges = <0x0 0xe182c000 0x800>;
511 reg = <0x600 0x200>;
527 reg = <0xe2018000 0x200>;
528 ranges = <0x0 0xe2018000 0x800>;
536 reg = <0x200 0x200>;
552 reg = <0x400 0x200>;
557 #size-cells = <0>;
568 reg = <0xe201c000 0x200>;
569 ranges = <0x0 0xe201c000 0x800>;
577 reg = <0x600 0x200>;
581 #size-cells = <0>;
592 reg = <0xe2020000 0x200>;
593 ranges = <0x0 0xe2020000 0x800>;
601 reg = <0x200 0x200>;
613 reg = <0xe2024000 0x200>;
614 ranges = <0x0 0xe2024000 0x800>;
622 reg = <0x200 0x200>;
639 reg = <0xe281c000 0x200>;
640 ranges = <0x0 0xe281c000 0x800>;
648 reg = <0x600 0x200>;
652 #size-cells = <0>;
663 reg = <0xe2820000 0x200>;
664 ranges = <0x0 0xe281c000 0x800>;
672 reg = <0x600 0x200>;
676 #size-cells = <0>;
687 reg = <0xe2824000 0x200>;
688 ranges = <0x0 0xe2824000 0x800>;
696 reg = <0x600 0x200>;
700 #size-cells = <0>;
708 reg = <0xe3800000 0x4000>;
713 reg = <0xe3804000 0x1000>;
718 reg = <0xe8c11000 0x1000>,
719 <0xe8c12000 0x2000>;
721 #address-cells = <0>;