Lines Matching +full:0 +full:xf0020000
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 d-cache-size = <0x8000>; // L1, 32 KB
36 i-cache-size = <0x8000>; // L1, 32 KB
43 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
48 reg = <0x740000 0x1000>;
64 reg = <0x73c000 0x1000>;
80 reg = <0x20000000 0x20000000>;
86 #clock-cells = <0>;
87 clock-frequency = <0>;
92 #clock-cells = <0>;
93 clock-frequency = <0>;
99 reg = <0x00200000 0x20000>;
102 ranges = <0 0x00200000 0x20000>;
124 reg = <0x00100000 0x2400>;
127 ranges = <0 0x00100000 0x2400>;
133 reg = <0x00300000 0x100000
134 0xfc02c000 0x400>;
143 reg = <0x00400000 0x100000>;
152 reg = <0x00500000 0x100000>;
161 reg = <0x00a00000 0x1000>;
165 cache-size = <0x20000>; // L2, 128 KB
173 reg = <0x10000000 0x10000000
174 0x60000000 0x30000000>;
175 ranges = <0x0 0x0 0x10000000 0x10000000
176 0x1 0x0 0x60000000 0x10000000
177 0x2 0x0 0x70000000 0x10000000
178 0x3 0x0 0x80000000 0x10000000>;
196 reg = <0xa0000000 0x300>;
197 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
207 reg = <0xb0000000 0x300>;
208 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
218 reg = <0xc0000000 0x8000000>;
229 reg = <0xf0000000 0x2000>;
230 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
238 #size-cells = <0>;
240 port@0 {
242 #size-cells = <0>;
243 reg = <0>;
255 reg = <0xf0008000 0x4000>;
259 #clock-cells = <0>;
266 reg = <0xf000c000 0x200>;
273 reg = <0xf0010000 0x1000>;
274 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
283 reg = <0xf0004000 0x1000>;
284 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
292 reg = <0xf0014000 0x160>;
301 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
307 #size-cells = <0>;
313 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
319 #size-cells = <0>;
325 reg = <0xf0028000 0x100>;
326 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
337 reg = <0xf002c000 0x100>;
338 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
343 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
352 reg = <0xf8000000 0x100>;
355 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
358 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
365 #size-cells = <0>;
371 reg = <0xf8004000 0x4000>;
374 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
377 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
387 reg = <0xf8008000 0x1000>;
388 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */
399 #size-cells = <0>;
400 reg = <0xf800c000 0x100>;
401 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
409 #size-cells = <0>;
410 reg = <0xf8010000 0x100>;
411 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
418 reg = <0xf8014000 0x1000>;
427 reg = <0xf8014070 0x490>,
428 <0xf8014500 0x200>;
434 reg = <0xf8018000 0x124>;
437 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
447 reg = <0xf801c000 0x100>;
451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
454 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
464 reg = <0xf8020000 0x100>;
468 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
471 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
481 reg = <0xf8024000 0x100>;
485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
488 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
498 reg = <0xf8028000 0x100>;
501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
502 AT91_XDMAC_DT_PERID(0))>,
504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
508 #size-cells = <0>;
516 reg = <0xf802c000 0x4000>;
525 reg = <0xf8030000 0x98>;
530 reg = <0xf8034000 0x200>;
534 ranges = <0x0 0xf8034000 0x800>;
539 reg = <0x200 0x200>;
545 (AT91_XDMAC_DT_MEM_IF(0) |
549 (AT91_XDMAC_DT_MEM_IF(0) |
559 reg = <0x400 0x200>;
562 #size-cells = <0>;
566 (AT91_XDMAC_DT_MEM_IF(0) |
570 (AT91_XDMAC_DT_MEM_IF(0) |
580 reg = <0x600 0x200>;
583 #size-cells = <0>;
586 (AT91_XDMAC_DT_MEM_IF(0) |
590 (AT91_XDMAC_DT_MEM_IF(0) |
601 reg = <0xf8038000 0x200>;
605 ranges = <0x0 0xf8038000 0x800>;
610 reg = <0x200 0x200>;
616 (AT91_XDMAC_DT_MEM_IF(0) |
620 (AT91_XDMAC_DT_MEM_IF(0) |
630 reg = <0x400 0x200>;
633 #size-cells = <0>;
637 (AT91_XDMAC_DT_MEM_IF(0) |
641 (AT91_XDMAC_DT_MEM_IF(0) |
651 reg = <0x600 0x200>;
654 #size-cells = <0>;
657 (AT91_XDMAC_DT_MEM_IF(0) |
661 (AT91_XDMAC_DT_MEM_IF(0) |
672 reg = <0xf8044000 0x1420>;
677 ranges = <0 0xf8044000 0x1420>;
682 reg = <0xf8048000 0x10>;
688 reg = <0xf8048010 0x10>;
691 #size-cells = <0>;
697 reg = <0xf8048030 0x10>;
704 reg = <0xf8048040 0x10>;
712 reg = <0xf8048050 0x4>;
714 #clock-cells = <0>;
719 reg = <0xf80480b0 0x30>;
726 reg = <0xf8050000 0x100>;
729 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
732 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
744 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
754 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
760 reg = <0xfc000000 0x100>;
763 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
766 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
773 #size-cells = <0>;
779 reg = <0xfc008000 0x100>;
783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
786 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
796 reg = <0xfc00c000 0x100>;
799 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
802 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
813 reg = <0xfc010000 0x200>;
817 ranges = <0x0 0xfc010000 0x800>;
822 reg = <0x200 0x200>;
828 (AT91_XDMAC_DT_MEM_IF(0) |
832 (AT91_XDMAC_DT_MEM_IF(0) |
842 reg = <0x400 0x200>;
845 #size-cells = <0>;
849 (AT91_XDMAC_DT_MEM_IF(0) |
853 (AT91_XDMAC_DT_MEM_IF(0) |
863 reg = <0x600 0x200>;
866 #size-cells = <0>;
869 (AT91_XDMAC_DT_MEM_IF(0) |
873 (AT91_XDMAC_DT_MEM_IF(0) |
884 reg = <0xfc014000 0x200>;
888 ranges = <0x0 0xfc014000 0x800>;
893 reg = <0x200 0x200>;
899 (AT91_XDMAC_DT_MEM_IF(0) |
903 (AT91_XDMAC_DT_MEM_IF(0) |
913 reg = <0x400 0x200>;
916 #size-cells = <0>;
920 (AT91_XDMAC_DT_MEM_IF(0) |
924 (AT91_XDMAC_DT_MEM_IF(0) |
934 reg = <0x600 0x200>;
937 #size-cells = <0>;
940 (AT91_XDMAC_DT_MEM_IF(0) |
944 (AT91_XDMAC_DT_MEM_IF(0) |
956 reg = <0xfc018000 0x200>;
960 ranges = <0x0 0xfc018000 0x800>;
965 reg = <0x200 0x200>;
971 (AT91_XDMAC_DT_MEM_IF(0) |
975 (AT91_XDMAC_DT_MEM_IF(0) |
985 reg = <0x400 0x200>;
988 #size-cells = <0>;
992 (AT91_XDMAC_DT_MEM_IF(0) |
996 (AT91_XDMAC_DT_MEM_IF(0) |
1006 reg = <0x600 0x200>;
1009 #size-cells = <0>;
1012 (AT91_XDMAC_DT_MEM_IF(0) |
1016 (AT91_XDMAC_DT_MEM_IF(0) |
1027 reg = <0xfc01c000 0x100>;
1028 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1036 reg = <0xfc020000 0x200>;
1042 reg = <0xfc028000 0x100>;
1045 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1048 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1052 #size-cells = <0>;
1060 reg = <0xfc030000 0x100>;
1064 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1076 reg = <0xfc038000 0x600>;
1090 reg = <0xfc040000 0x100>;
1098 reg = <0xfc044000 0x100>;
1099 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1104 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1113 reg = <0xfc048000 0x100>;
1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1126 reg = <0xfc04c000 0x100>;
1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1144 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1154 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1160 reg = <0xfc05c000 0x20>;
1165 reg = <0xfc069000 0x8>;