Lines Matching +full:0 +full:xf0020000
36 #size-cells = <0>;
38 cpu@0 {
40 reg = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
61 reg = <0x300000 0x10000>;
62 ranges = <0 0x300000 0x10000>;
75 reg = <0x80000000 0x300>;
76 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
86 reg = <0x90000000 0x300>;
87 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
104 reg = <0xf0000000 0x200>;
105 ranges = <0x0 0xf0000000 0x800>;
113 reg = <0x200 0x200>;
118 (AT91_XDMAC_DT_MEM_IF(0) |
122 (AT91_XDMAC_DT_MEM_IF(0) |
135 reg = <0x400 0x200>;
138 #size-cells = <0>;
142 (AT91_XDMAC_DT_MEM_IF(0) |
146 (AT91_XDMAC_DT_MEM_IF(0) |
156 reg = <0x600 0x200>;
159 #size-cells = <0>;
162 (AT91_XDMAC_DT_MEM_IF(0) |
166 (AT91_XDMAC_DT_MEM_IF(0) |
177 reg = <0xf0004000 0x200>;
178 ranges = <0x0 0xf0004000 0x800>;
186 reg = <0x200 0x200>;
191 (AT91_XDMAC_DT_MEM_IF(0) |
195 (AT91_XDMAC_DT_MEM_IF(0) |
208 reg = <0x400 0x200>;
211 #size-cells = <0>;
215 (AT91_XDMAC_DT_MEM_IF(0) |
219 (AT91_XDMAC_DT_MEM_IF(0) |
229 reg = <0x600 0x200>;
232 #size-cells = <0>;
235 (AT91_XDMAC_DT_MEM_IF(0) |
239 (AT91_XDMAC_DT_MEM_IF(0) |
250 reg = <0xf0008000 0x1000>;
251 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
260 reg = <0xf0010000 0x4000>;
265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
268 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
276 reg = <0xf001c000 0x100>;
281 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
284 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
292 reg = <0xf0020000 0x200>;
293 ranges = <0x0 0xf0020000 0x800>;
301 reg = <0x200 0x200>;
306 (AT91_XDMAC_DT_MEM_IF(0) |
310 (AT91_XDMAC_DT_MEM_IF(0) |
323 reg = <0x600 0x200>;
326 #size-cells = <0>;
329 (AT91_XDMAC_DT_MEM_IF(0) |
333 (AT91_XDMAC_DT_MEM_IF(0) |
344 reg = <0xf0024000 0x200>;
345 ranges = <0x0 0xf0024000 0x800>;
353 reg = <0x200 0x200>;
358 (AT91_XDMAC_DT_MEM_IF(0) |
362 (AT91_XDMAC_DT_MEM_IF(0) |
375 reg = <0x600 0x200>;
378 #size-cells = <0>;
381 (AT91_XDMAC_DT_MEM_IF(0) |
385 (AT91_XDMAC_DT_MEM_IF(0) |
396 reg = <0xf0028000 0x100>;
404 reg = <0xf002c000 0x100>;
405 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
409 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
416 reg = <0xf0030000 0x100>;
417 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
424 reg = <0xf0034000 0x100>;
425 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
429 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
432 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
439 reg = <0xf0038000 0x100>;
440 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
454 reg = <0xf003c000 0x100>;
459 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
467 reg = <0xf0040000 0x100>;
475 reg = <0xf8000000 0x100>, <0x300000 0x7800>;
477 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>,
478 <68 IRQ_TYPE_LEVEL_HIGH 0>;
485 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
491 reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
493 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>,
494 <69 IRQ_TYPE_LEVEL_HIGH 0>;
501 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
507 reg = <0xf8008000 0x100>;
509 #size-cells = <0>;
510 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
511 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>;
517 reg = <0xf8010000 0x200>;
518 ranges = <0x0 0xf8010000 0x800>;
526 reg = <0x200 0x200>;
531 (AT91_XDMAC_DT_MEM_IF(0) |
535 (AT91_XDMAC_DT_MEM_IF(0) |
548 reg = <0x600 0x200>;
551 #size-cells = <0>;
554 (AT91_XDMAC_DT_MEM_IF(0) |
558 (AT91_XDMAC_DT_MEM_IF(0) |
569 reg = <0xf8014000 0x200>;
570 ranges = <0x0 0xf8014000 0x800>;
578 reg = <0x200 0x200>;
583 (AT91_XDMAC_DT_MEM_IF(0) |
587 (AT91_XDMAC_DT_MEM_IF(0) |
600 reg = <0x600 0x200>;
603 #size-cells = <0>;
606 (AT91_XDMAC_DT_MEM_IF(0) |
610 (AT91_XDMAC_DT_MEM_IF(0) |
621 reg = <0xf8018000 0x200>;
622 ranges = <0x0 0xf8018000 0x800>;
630 reg = <0x200 0x200>;
635 (AT91_XDMAC_DT_MEM_IF(0) |
639 (AT91_XDMAC_DT_MEM_IF(0) |
652 reg = <0x600 0x200>;
655 #size-cells = <0>;
658 (AT91_XDMAC_DT_MEM_IF(0) |
662 (AT91_XDMAC_DT_MEM_IF(0) |
673 reg = <0xf801c000 0x200>;
674 ranges = <0x0 0xf801c000 0x800>;
682 reg = <0x200 0x200>;
687 (AT91_XDMAC_DT_MEM_IF(0) |
689 AT91_XDMAC_DT_PERID(0))>,
691 (AT91_XDMAC_DT_MEM_IF(0) |
704 reg = <0x400 0x200>;
707 #size-cells = <0>;
711 (AT91_XDMAC_DT_MEM_IF(0) |
713 AT91_XDMAC_DT_PERID(0))>,
715 (AT91_XDMAC_DT_MEM_IF(0) |
725 reg = <0x600 0x200>;
728 #size-cells = <0>;
731 (AT91_XDMAC_DT_MEM_IF(0) |
733 AT91_XDMAC_DT_PERID(0))>,
735 (AT91_XDMAC_DT_MEM_IF(0) |
746 reg = <0xf8020000 0x200>;
747 ranges = <0x0 0xf8020000 0x800>;
755 reg = <0x200 0x200>;
760 (AT91_XDMAC_DT_MEM_IF(0) |
764 (AT91_XDMAC_DT_MEM_IF(0) |
777 reg = <0x400 0x200>;
780 #size-cells = <0>;
784 (AT91_XDMAC_DT_MEM_IF(0) |
788 (AT91_XDMAC_DT_MEM_IF(0) |
798 reg = <0x600 0x200>;
801 #size-cells = <0>;
804 (AT91_XDMAC_DT_MEM_IF(0) |
808 (AT91_XDMAC_DT_MEM_IF(0) |
819 reg = <0xf8024000 0x200>;
820 ranges = <0x0 0xf8024000 0x800>;
828 reg = <0x200 0x200>;
833 (AT91_XDMAC_DT_MEM_IF(0) |
837 (AT91_XDMAC_DT_MEM_IF(0) |
850 reg = <0x400 0x200>;
853 #size-cells = <0>;
857 (AT91_XDMAC_DT_MEM_IF(0) |
861 (AT91_XDMAC_DT_MEM_IF(0) |
871 reg = <0x600 0x200>;
874 #size-cells = <0>;
877 (AT91_XDMAC_DT_MEM_IF(0) |
881 (AT91_XDMAC_DT_MEM_IF(0) |
892 reg = <0xf8028000 0x200>;
893 ranges = <0x0 0xf8028000 0x800>;
901 reg = <0x200 0x200>;
906 (AT91_XDMAC_DT_MEM_IF(0) |
910 (AT91_XDMAC_DT_MEM_IF(0) |
923 reg = <0x400 0x200>;
926 #size-cells = <0>;
930 (AT91_XDMAC_DT_MEM_IF(0) |
934 (AT91_XDMAC_DT_MEM_IF(0) |
944 reg = <0x600 0x200>;
947 #size-cells = <0>;
950 (AT91_XDMAC_DT_MEM_IF(0) |
954 (AT91_XDMAC_DT_MEM_IF(0) |
965 reg = <0xf802c000 0x1000>;
966 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */
981 reg = <0xf8034000 0x300>;
990 reg = <0xf8038000 0x4000>;
991 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
999 #size-cells = <0>;
1001 port@0 {
1002 reg = <0>;
1004 #size-cells = <0>;
1016 reg = <0xf8040000 0x200>;
1017 ranges = <0x0 0xf8040000 0x800>;
1025 reg = <0x200 0x200>;
1030 (AT91_XDMAC_DT_MEM_IF(0) |
1034 (AT91_XDMAC_DT_MEM_IF(0) |
1047 reg = <0x600 0x200>;
1050 #size-cells = <0>;
1053 (AT91_XDMAC_DT_MEM_IF(0) |
1057 (AT91_XDMAC_DT_MEM_IF(0) |
1068 reg = <0xf8044000 0x200>;
1069 ranges = <0x0 0xf8044000 0x800>;
1077 reg = <0x200 0x200>;
1082 (AT91_XDMAC_DT_MEM_IF(0) |
1086 (AT91_XDMAC_DT_MEM_IF(0) |
1099 reg = <0x600 0x200>;
1102 #size-cells = <0>;
1105 (AT91_XDMAC_DT_MEM_IF(0) |
1109 (AT91_XDMAC_DT_MEM_IF(0) |
1120 reg = <0xf8060000 0x100>;
1121 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>;
1129 reg = <0xffffde00 0x200>;
1134 reg = <0xffffe000 0x300>, <0xffffe600 0x100>;
1139 reg = <0xffffe800 0x200>;
1146 reg = <0xffffea00 0x100>;
1151 reg = <0xfffff100 0x100>;
1159 reg = <0xfffff200 0x200>;
1164 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1167 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1176 ranges = <0xfffff400 0xfffff400 0x800>;
1183 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */
1184 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */
1185 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */
1186 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */
1191 reg = <0xfffff400 0x200>;
1202 reg = <0xfffff600 0x200>;
1214 reg = <0xfffff800 0x200>;
1225 reg = <0xfffffa00 0x200>;
1238 reg = <0xfffffc00 0x200>;
1241 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
1247 reg = <0xfffffe00 0x10>;
1248 clocks = <&clk32k 0>;
1253 reg = <0xfffffe10 0x10>;
1255 #size-cells = <0>;
1256 clocks = <&clk32k 0>;
1264 reg = <0xfffffe20 0x20>;
1266 clocks = <&clk32k 0>;
1271 reg = <0xfffffe50 0x4>;
1278 reg = <0xfffffe60 0x10>;
1283 reg = <0xfffffea8 0x100>;
1285 clocks = <&clk32k 0>;
1290 reg = <0xffffff80 0x24>;