Lines Matching refs:deadlock

573 	bool "ARM errata: Processor deadlock when a false hazard is created"
581 	  hazard might then cause a processor deadlock. The workaround enables
751        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
757 	 to deadlock. This workaround puts DSB before executing ISB if
780 	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
785 	    instruction might deadlock.  Fixed in r0p1.
787 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
801 	  deadlock when the VMOV instructions are issued out-of-order.
804 	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
810 	  and Device/Strongly-Ordered loads and stores might cause deadlock
813 	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
830 	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
835 	    lead to either a data corruption or a CPU deadlock.  Not fixed in
842 	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"