Lines Matching refs:PTP
450 a HW PTP clock source, to allow time conversion in userspace and
451 optionally synchronize system time with a userspace PTP stack such
452 as linuxptp. For the PTP clock API, see Documentation/driver-api/ptp.rst.
618 /* PTP v1, UDP, any kind of event packet */
674 3.2 Special considerations for stacked PTP Hardware Clocks
677 There are situations when there may be more than one PHC (PTP Hardware Clock)
694 When a DSA switch is attached to a host port, PTP synchronization has to
696 jitter between the host port and its PTP partner. For this reason, some DSA
705 By design, PTP timestamping with a DSA switch does not need any special
707 host port also supports PTP timestamping, DSA will take care of intercepting
713 In the generic layer, DSA provides the following infrastructure for PTP
725 PTP TX timestamp register (or sometimes a FIFO) where the timestamp
727 key-value pairs of PTP sequence ID/message type/domain number and the
731 the PTP transport type, and ``ptp_parse_header`` to interpret the PTP
736 no follow-up message required by the PTP protocol (because the
742 identify PTP event messages (any other packets, including PTP general
758 switches do. However, PHYs may be able to detect and timestamp PTP packets, for
762 A PHY driver that supports PTP timestamping must create a ``struct
827 1. "TX": checks whether PTP timestamping has been previously enabled through
848 that PTP timestamping is not enabled for anything other than the outermost PHC,