Lines Matching +full:lpassaudiocc +full:- +full:sc7280
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - enum:
20 - qcom,soundwire-v1.3.0
21 - qcom,soundwire-v1.5.0
22 - qcom,soundwire-v1.5.1
23 - qcom,soundwire-v1.6.0
24 - qcom,soundwire-v1.7.0
25 - qcom,soundwire-v2.0.0
26 - items:
27 - enum:
28 - qcom,soundwire-v2.1.0
29 - const: qcom,soundwire-v2.0.0
37 - description: specify the SoundWire controller core.
38 - description: specify the Soundwire controller wake IRQ.
40 interrupt-names:
43 - const: core
44 - const: wakeup
48 - description: iface clock
50 clock-names:
52 - const: iface
56 - description: SWR_AUDIO_CGCR RESET
58 reset-names:
60 - const: swr_audio_cgcr
62 '#sound-dai-cells':
65 '#address-cells':
68 '#size-cells':
71 wakeup-source: true
73 qcom,din-ports:
77 qcom,dout-ports:
81 qcom,ports-word-length:
82 $ref: /schemas/types.yaml#/definitions/uint8-array
91 qcom,ports-sinterval-low:
92 $ref: /schemas/types.yaml#/definitions/uint8-array
102 qcom,ports-sinterval:
103 $ref: /schemas/types.yaml#/definitions/uint16-array
113 qcom,ports-offset1:
114 $ref: /schemas/types.yaml#/definitions/uint8-array
124 qcom,ports-offset2:
125 $ref: /schemas/types.yaml#/definitions/uint8-array
135 qcom,ports-lane-control:
136 $ref: /schemas/types.yaml#/definitions/uint8-array
146 qcom,ports-block-pack-mode:
147 $ref: /schemas/types.yaml#/definitions/uint8-array
160 - minimum: 0
162 - const: 0xff
164 qcom,ports-hstart:
165 $ref: /schemas/types.yaml#/definitions/uint8-array
168 i.e. left edge of the Transport sub-frame for each port.
177 - minimum: 0
179 - const: 0xff
181 qcom,ports-hstop:
182 $ref: /schemas/types.yaml#/definitions/uint8-array
186 sub-frame for each port. Out ports followed by In ports.
194 - minimum: 0
196 - const: 0xff
198 qcom,ports-block-group-count:
199 $ref: /schemas/types.yaml#/definitions/uint8-array
210 - minimum: 0
212 - const: 0xff
218 - compatible
219 - reg
220 - interrupts
221 - clocks
222 - clock-names
223 - '#sound-dai-cells'
224 - '#address-cells'
225 - '#size-cells'
226 - qcom,dout-ports
227 - qcom,din-ports
228 - qcom,ports-offset1
229 - qcom,ports-offset2
232 - required:
233 - qcom,ports-sinterval-low
234 - required:
235 - qcom,ports-sinterval
238 - $ref: soundwire-controller.yaml#
243 - |
244 #include <dt-bindings/interrupt-controller/arm-gic.h>
245 #include <dt-bindings/interrupt-controller/irq.h>
246 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
249 compatible = "qcom,soundwire-v1.6.0";
255 interrupt-names = "core", "wakeup";
258 clock-names = "iface";
260 qcom,din-ports = <0>;
261 qcom,dout-ports = <5>;
264 reset-names = "swr_audio_cgcr";
266 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
267 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
268 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
269 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
270 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
271 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
272 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
273 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
274 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
276 #sound-dai-cells = <1>;
277 #address-cells = <2>;
278 #size-cells = <0>;
283 qcom,rx-port-mapping = <1 2 3 4 5>;