Lines Matching +full:0 +full:xd2000000

15   byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
46 		reg = <0xd1800000 0x1000	/* FSMC Register */
47 		       0xd2000000 0x0010	/* NAND Base DATA */
48 		       0xd2020000 0x0010	/* NAND Base ADDR */
49 		       0xd2010000 0x0010>;	/* NAND Base CMD */
54 		timings = /bits/ 8 <0 0 0 2 3 0>;
57 		partition@0 {