bindings/firmware/nvidia%2Ctegra186-bpmp.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Thierry Reding <thierry.reding@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
25     - .../mailbox/mailbox.txt
26     - .../mailbox/nvidia,tegra186-hsp.yaml
32     - .../clock/clock-bindings.txt
33     - <dt-bindings/clock/tegra186-clock.h>
34     - ../power/power-domain.yaml
35     - <dt-bindings/power/tegra186-powergate.h>
36     - .../reset/reset.txt
37     - <dt-bindings/reset/tegra186-reset.h>
49   provide configuration information regarding the BPMP itself, although
50   no such configuration nodes are currently defined by this binding.
52   The BPMP firmware defines no single global name-/numbering-space for
57   "#address-cells" or "#size-cells" property.
63   See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
69       - items:
70           - enum:
71               - nvidia,tegra194-bpmp
72               - nvidia,tegra234-bpmp
73               - nvidia,tegra264-bpmp
74           - const: nvidia,tegra186-bpmp
75       - const: nvidia,tegra186-bpmp
88   memory-region:
90       CPU-NS and BPMP.
93   "#clock-cells":
96   "#power-domain-cells":
99   "#reset-cells":
104       - description: memory read client
105       - description: memory write client
106       - description: DMA read client
107       - description: DMA write client
109   interconnect-names:
111       - const: read
112       - const: write
113       - const: dma-mem # dma-read
114       - const: dma-write
128   - required:
129       - memory-region
130   - required:
131       - shmem
134   - compatible
135   - mboxes
136   - "#clock-cells"
137   - "#power-domain-cells"
138   - "#reset-cells"
141   - |
142     #include <dt-bindings/interrupt-controller/arm-gic.h>
143     #include <dt-bindings/mailbox/tegra186-hsp.h>
144     #include <dt-bindings/memory/tegra186-mc.h>
147         compatible = "nvidia,tegra186-hsp";
150         interrupt-names = "doorbell";
151         #mbox-cells = <2>;
155         compatible = "nvidia,tegra186-sysram", "mmio-sram";
157         #address-cells = <1>;
158         #size-cells = <1>;
163             label = "cpu-bpmp-tx";
169             label = "cpu-bpmp-rx";
175         compatible = "nvidia,tegra186-bpmp";
176         interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
177                         <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
178                         <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
179                         <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
180         interconnect-names = "read", "write", "dma-mem", "dma-write";
184         #clock-cells = <1>;
185         #power-domain-cells = <1>;
186         #reset-cells = <1>;
189             compatible = "nvidia,tegra186-bpmp-i2c";
190             nvidia,bpmp-bus-id = <5>;
191             #address-cells = <1>;
192             #size-cells = <0>;
196             compatible = "nvidia,tegra186-bpmp-thermal";
197             #thermal-sensor-cells = <1>;
201   - |
202     #include <dt-bindings/mailbox/tegra186-hsp.h>
205         compatible = "nvidia,tegra186-bpmp";
206         interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
207                         <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
208                         <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
209                         <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
210         interconnect-names = "read", "write", "dma-mem", "dma-write";
212         memory-region = <&dram_cpu_bpmp_mail>;
213         #clock-cells = <1>;
214         #power-domain-cells = <1>;
215         #reset-cells = <1>;