Lines Matching +full:rk3588 +full:- +full:cru
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <heiko@sntech.de>
17 - Andy Yan <andyshrk@163.com>
22 - rockchip,rk3566-vop
23 - rockchip,rk3568-vop
24 - rockchip,rk3576-vop
25 - rockchip,rk3588-vop
29 - description:
32 - description:
36 reg-names:
38 - const: vop
39 - const: gamma-lut
51 interrupt-names:
53 - const: sys
54 - const: vp0
55 - const: vp1
56 - const: vp2
58 # See compatible-specific constraints below.
62 - description: Clock for ddr buffer transfer via axi.
63 - description: Clock for the ahb bus to R/W the regs.
64 - description: Pixel clock for video port 0.
65 - description: Pixel clock for video port 1.
66 - description: Pixel clock for video port 2.
67 - {}
68 - {}
69 - {}
70 - {}
72 clock-names:
75 - const: aclk
76 - const: hclk
77 - const: dclk_vp0
78 - const: dclk_vp1
79 - const: dclk_vp2
80 - {}
81 - {}
82 - {}
83 - {}
91 rockchip,vo1-grf:
95 on rk3588.
97 rockchip,vop-grf:
105 Phandle to PMU GRF used for query vop memory bisr status on rk3588.
111 "^port@[0-3]$":
116 - port@0
123 power-domains:
127 - compatible
128 - reg
129 - reg-names
130 - interrupts
131 - clocks
132 - clock-names
133 - ports
136 - if:
141 - rockchip,rk3566-vop
142 - rockchip,rk3568-vop
148 clock-names:
154 interrupt-names: false
158 - port@0
159 - port@1
160 - port@2
162 rockchip,vo1-grf: false
163 rockchip,vop-grf: false
167 - rockchip,grf
169 - if:
174 - rockchip,rk3576-vop
180 - {}
181 - {}
182 - {}
183 - {}
184 - {}
185 - description: Alternative pixel clock provided by HDMI PHY PLL.
187 clock-names:
190 - {}
191 - {}
192 - {}
193 - {}
194 - {}
195 - const: pll_hdmiphy0
200 interrupt-names:
205 - port@0
206 - port@1
207 - port@2
209 rockchip,vo1-grf: false
210 rockchip,vop-grf: false
213 - rockchip,grf
214 - rockchip,pmu
216 - if:
220 const: rockchip,rk3588-vop
226 - {}
227 - {}
228 - {}
229 - {}
230 - {}
231 - description: Pixel clock for video port 3.
232 - description: Peripheral(vop grf/dsi) clock.
233 - description: Alternative pixel clock provided by HDMI0 PHY PLL.
234 - description: Alternative pixel clock provided by HDMI1 PHY PLL.
236 clock-names:
239 - {}
240 - {}
241 - {}
242 - {}
243 - {}
244 - const: dclk_vp3
245 - const: pclk_vop
246 - const: pll_hdmiphy0
247 - const: pll_hdmiphy1
252 interrupt-names: false
256 - port@0
257 - port@1
258 - port@2
259 - port@3
262 - rockchip,grf
263 - rockchip,vo1-grf
264 - rockchip,vop-grf
265 - rockchip,pmu
270 - |
271 #include <dt-bindings/clock/rk3568-cru.h>
272 #include <dt-bindings/interrupt-controller/arm-gic.h>
273 #include <dt-bindings/power/rk3568-power.h>
275 #address-cells = <2>;
276 #size-cells = <2>;
278 compatible = "rockchip,rk3568-vop";
280 reg-names = "vop", "gamma-lut";
282 clocks = <&cru ACLK_VOP>,
283 <&cru HCLK_VOP>,
284 <&cru DCLK_VOP0>,
285 <&cru DCLK_VOP1>,
286 <&cru DCLK_VOP2>;
287 clock-names = "aclk",
292 power-domains = <&power RK3568_PD_VO>;
296 #address-cells = <1>;
297 #size-cells = <0>;
300 #address-cells = <1>;
301 #size-cells = <0>;
305 #address-cells = <1>;
306 #size-cells = <0>;
310 #address-cells = <1>;
311 #size-cells = <0>;