Lines Matching +full:0 +full:x0ae96000

43   "^display-controller@[0-9a-f]+$":
50   "^displayport-controller@[0-9a-f]+$":
58   "^dsi@[0-9a-f]+$":
66   "^phy@[0-9a-f]+$":
86         reg = <0x0ae00000 0x1000>;
107         iommus = <&apps_smmu 0x1c00 0x2>;
115             reg = <0x0ae01000 0x8f000>,
116                   <0x0aeb0000 0x2008>;
139             interrupts = <0>;
143                 #size-cells = <0>;
145                 port@0 {
146                     reg = <0>;
198             reg = <0xae90000 0x200>,
199                   <0xae90200 0x200>,
200                   <0xae90400 0xc00>,
201                   <0xae91000 0x400>,
202                   <0xae91400 0x400>;
225             #sound-dai-cells = <0>;
232                 #size-cells = <0>;
234                 port@0 {
235                     reg = <0>;
277             reg = <0x0ae94000 0x400>;
298             assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
307             #size-cells = <0>;
311                 #size-cells = <0>;
313                 port@0 {
314                     reg = <0>;
351             reg = <0x0ae95000 0x200>,
352                   <0x0ae95200 0x280>,
353                   <0x0ae95500 0x400>;
359             #phy-cells = <0>;
369             reg = <0x0ae96000 0x400>;
390             assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
399             #size-cells = <0>;
403                 #size-cells = <0>;
405                 port@0 {
406                     reg = <0>;
424             reg = <0x0ae97000 0x200>,
425                   <0x0ae97200 0x280>,
426                   <0x0ae97500 0x400>;
432             #phy-cells = <0>;