Lines Matching +full:0 +full:xaf55000
38 "^display-controller@[0-9a-f]+$":
46 "^displayport-controller@[0-9a-f]+$":
55 "^dsi@[0-9a-f]+$":
63 "^phy@[0-9a-f]+$":
90 reg = <0x0ae00000 0x1000>;
111 iommus = <&apps_smmu 0x1000 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
141 interrupts = <0>;
145 #size-cells = <0>;
147 port@0 {
148 reg = <0>;
197 reg = <0x0aec2a00 0x200>,
198 <0x0aec2200 0xd0>,
199 <0x0aec2600 0xd0>,
200 <0x0aec2000 0x1c8>;
208 #phy-cells = <0>;
216 reg = <0x0ae94000 0x400>;
236 assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>;
243 #size-cells = <0>;
247 #size-cells = <0>;
249 port@0 {
250 reg = <0>;
274 reg = <0x0ae94400 0x200>,
275 <0x0ae94600 0x280>,
276 <0x0ae94900 0x27c>;
282 #phy-cells = <0>;
293 reg = <0x0ae96000 0x400>;
313 assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>;
320 #size-cells = <0>;
324 #size-cells = <0>;
326 port@0 {
327 reg = <0>;
351 reg = <0x0ae96400 0x200>,
352 <0x0ae96600 0x280>,
353 <0x0ae96900 0x27c>;
359 #phy-cells = <0>;
371 pinctrl-0 = <&dp_hot_plug_det>;
374 reg = <0xaf54000 0x104>,
375 <0xaf54200 0x0c0>,
376 <0xaf55000 0x770>,
377 <0xaf56000 0x09c>,
378 <0xaf57000 0x09c>;
396 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
404 #sound-dai-cells = <0>;
408 #size-cells = <0>;
410 port@0 {
411 reg = <0>;