admin-guide/media/mgb4.rst

1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| 2023 - 2025 Digiteq Automotive
12 card capable of capturing and generating FPD-Link III and GMSL2/3 video streams
16 ---------------
22 There are two types of parameters - global / PCI card related, found under
32     | 0 - No module present
33     | 1 - FPDL3
34     | 2 - GMSL (one serializer, two daisy chained deserializers)
35     | 3 - GMSL (one serializer, two deserializers)
36     | 4 - GMSL (two deserializers with two daisy chain outputs)
44     | 1 - FPDL3
45     | 2 - GMSL
53         PRODUCT-REVISION-SERIES-SERIAL
61     Input number ID, zero based.
66     | 0 - single
67     | 1 - dual (default)
70     Mapping of the incoming bits in the signal to the colour bits of the pixels.
72     | 0 - OLDI/JEIDA
73     | 1 - SPWG/VESA (default)
83     | 0 - unlocked
84     | 1 - locked
88     pixel clock is running and the DE signal is moving.
93     | 0 - not detected
94     | 1 - detected
114     | 0 - active low
115     | 1 - active high
116     | 2 - not available
124     | 0 - active low
125     | 1 - active high
126     | 2 - not available
129     If the incoming video signal does not contain synchronization VSYNC and
132     (pixels with deasserted Data Enable signal) are necessary to generate the
136     If the incoming video signal does not contain synchronization VSYNC and
139     (pixels with deasserted Data Enable signal) are necessary to generate the
153     Width of the HSYNC signal in PCLK clock ticks.
159     Width of the VSYNC signal in PCLK clock ticks.
165     Number of PCLK pulses between deassertion of the HSYNC signal and the first
173     line (marked by DE=1) and assertion of the HSYNC signal.
179     Number of video lines between deassertion of the VSYNC signal and the video
187     by DE=1) and assertion of the VSYNC signal.
198     | 0 - PLL < 50MHz (default)
199     | 1 - PLL >= 50MHz
208     Output number ID, zero based.
216     | 0 - input 0
217     | 1 - input 1
218     | 2 - v4l2 output 0
219     | 3 - v4l2 output 1
241     Output video signal frame rate limit in frames per second. Due to
244     Using this parameter one can limit the frame rate by "crippling" the signal
246     the signal appears like having the exact frame rate to the connected display.
250     HSYNC signal polarity.
252     | 0 - active low (default)
253     | 1 - active high
256     VSYNC signal polarity.
258     | 0 - active low (default)
259     | 1 - active high
262     DE signal polarity.
264     | 0 - active low
265     | 1 - active high (default)
268     Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
269     and there is a non-linear stepping between two consecutive allowed
278     Width of the HSYNC signal in pixels. The default value is 40.
281     Width of the VSYNC signal in video lines. The default value is 20.
284     Number of PCLK pulses between deassertion of the HSYNC signal and the first
289     line (marked by DE=1) and assertion of the HSYNC signal. The default value
293     Number of video lines between deassertion of the VSYNC signal and the video
298     by DE=1) and assertion of the VSYNC signal. The default value is 30.
306     | 0 - auto (default)
307     | 1 - single
308     | 2 - dual
316     | 0 - auto (default)
317     | 1 - single
318     | 2 - dual
326     | 0 - 12Gb/s (default)
327     | 1 - 6Gb/s
328     | 2 - 3Gb/s
329     | 3 - 1.5Gb/s
332     The GMSL multi-stream contains up to four video streams. This parameter
334     zero-based index of the stream. The default stream id is 0.
342     | 0 - disabled
343     | 1 - enabled (default)
346 --------------
349  - mgb4-fw.X - FPGA firmware.
350  - mgb4-data.X - Factory settings, e.g. card serial number.
352 The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
353 read-only. The *X* attached to the partition name represents the card number.
355 also have a third partition named *mgb4-flash* available in the system. This
360 --------------
363 signal level status capability. The following scan elements are available:
368 	| bit 1 - trigger 1 pending
369 	| bit 2 - trigger 2 pending
370 	| bit 5 - trigger 1 level
371 	| bit 6 - trigger 2 level
376 The iio device can operate either in "raw" mode where you can fetch the signal
378 In the triggered buffer mode you can follow the signal level changes (activity
385 buffer mode - the values do not represent valid data in such case.*