Lines Matching +full:0 +full:x22

74 // bits 15: 0	pid
83 0:	str	w2, [x0], #4
86 	bne	0b
163 	and	w0, w0, #0x3
176 	mov	x0, #0
195 	stp	x0, x1, [sp, #-0x20]!
196 	str	x2, [sp, #0x10]
198 	mov	x5, #0
199 0:	ldrb	w3, [x0, x5]
205 	b.ne	0b
207 1:	ldr	x2, [sp, #0x10]
208 	ldp	x0, x1, [sp], #0x20
280 	mov	x0, #0
340 	mov	x0, #0
342 	svc	#0
364 	mov	x2, #0
367 	svc	#0
381 	mov	x23, #0		// Irritation signal count
433 	svc	#0
444 	mov	x22, #0		// generation number, increments per iteration
450 	mov	x21, #0		// Set up Z-regs & shadow with test pattern
451 0:	mov	x0, x20
453 	and	x2, x22, #0xf
457 	b.lo	0b
461 	and	x2, x22, #0xf
464 0:	mov	x0, x20		// Set up P-regs & shadow with test pattern
466 	and	x2, x22, #0xf
470 	b.lo	0b
474 //	svc	#0
477 	mrs	x0, S3_3_C4_C2_2	// SVCR should have ZA=0,SM=1
483 	mov	x21, #0
484 0:	mov	x0, x21
488 	b.lo	0b
490 0:	mov	x0, x21
494 	b.lo	0b
498 	add	x22, x22, #1
502 	mov	x0, #0
505 	svc	#0
510 //	ldr	w0, =0xdeadc0de
512 //	svc	#0
526 	mov	x0, x22
548 	svc	#0
550 //	ldr	w0, =0xdeadc0de
552 //	svc	#0
556 	svc	#0
559 //	svc	#0
571 	svc	#0
583 	svc	#0