x86/emeraldrapids/frontend.json

3         "BriefDescription": "Clears due to Unknown Branches.",
6 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
14 …to dynamically changing prefix length of the decoded instruction (by operand size prefix instructi…
26         "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
29 …-cache that holds translations of previously fetched instructions that were decoded by the legacy …
40 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
51 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
89         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
95 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
100 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
106 …after an interval where the front-end delivered no uops for a period of 128 cycles which was not i…
111 … after an interval where the front-end delivered no uops for a period of 16 cycles which was not i…
117 …structions that are delivered to the back-end after a front-end stall of at least 16 cycles. Durin…
122         "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
128 …er an interval where the front-end delivered no uops for a period of at least 2 cycles which was n…
133 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
139 …after an interval where the front-end delivered no uops for a period of 256 cycles which was not i…
144 …er an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was n…
150 …t are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 c…
155 … after an interval where the front-end delivered no uops for a period of 32 cycles which was not i…
161 …structions that are delivered to the back-end after a front-end stall of at least 32 cycles. Durin…
166 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
172 … after an interval where the front-end delivered no uops for a period of 4 cycles which was not in…
177 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
183 …after an interval where the front-end delivered no uops for a period of 512 cycles which was not i…
188 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
194 … after an interval where the front-end delivered no uops for a period of 64 cycles which was not i…
199 … after an interval where the front-end delivered no uops for a period of 8 cycles which was not in…
205 …nstructions that are delivered to the back-end after a front-end stall of at least 8 cycles. Durin…
241 …      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
244 …"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction ca…
249 …  "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
252 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
261 …"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue …
270 …": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Deco…
275 …"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffe…
278 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
287 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
296 …": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Deco…
301         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
304 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
309         "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
313 …"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Qu…
318         "BriefDescription": "Number of switches from DSB or MITE to the MS",
323 … switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequen…
328         "BriefDescription": "Uops delivered to IDQ while MS is busy",
336 …red by IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVER…
339 …to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-en…
344 …by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVER…
348 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
353 …en optimal number of uops was delivered to the back-end when the back-end is not stalled [This eve…
358 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
363 …vered by IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]",
366 …to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-en…
371 …by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0…
375 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…
380 …en optimal number of uops was delivered to the back-end when the back-end is not stalled [This eve…
385 …DQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one S…