powerpc/power9/pipeline.json

10     "BriefDescription": "Number of I-ERAT reloads"
15 …te that this count is per slice, so if a load spans multiple slices this event will increment mult…
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
30 …scription": "The processor's data cache was reloaded either shared or modified data from another c…
35 …ription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node o…
40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
80 …ription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L…
90 …riefDescription": "The processor's data cache was reloaded from another chip's L4 on a different N…
95 …escription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core'…
100 …rbitration onto the issue pipe to another instruction (from the same thread or a different thread)"
105     "BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt"
115 …ption": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflict…
140     "BriefDescription": "IERAT Reloaded (Miss) for a 16M page"
150     "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch"
160 …A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L…
175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch…
180 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
185 …"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's …
190 …The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the…
200     "BriefDescription": "Non-speculative icache miss, counted at completion"
225 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl…
235 …The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the…
245 …"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the cor…
250 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on th…
255 …"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruct…
260 …A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on …
265 …ription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node …
270 …cription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch confl…
285 …riefDescription": "The processor's data cache was reloaded from another chip's memory on the same …
305 …cles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load"
310 …A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on …
320     "BriefDescription": "Threshold counter exceeded a value of 2048"
325 …"The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the …
350 …"BriefDescription": "The processor's Instruction cache was reloaded from a memory location includi…
380 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a …
390 …n": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's…
395 …Description": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's…
400 …ription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L…
435 …BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core…
440 …"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction…
450 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a mark…
460 …fDescription": "Finish stall because the NTF instruction was a load or store that suffered a trans…
480 …efDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch…
490 …iption": "A Page Table Entry was loaded into the TLB from a memory location including L4 from loca…
515 …BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core…
530 …cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load"