Lines Matching +full:processor +full:- +full:a +full:- +full:side

5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
10 … allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks …
15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi…
20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p…
25 …n cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and…
40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data…
45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its …
50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the …
55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
60 "BriefDescription": "Threshold counter exceeded a value of 128"
70 …ption": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conf…
75 "BriefDescription": "Threshold counter exceed a count of 4096"
80 …ription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node …
85 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl…
90 …"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older stor…
100 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
105 … "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"