perf/Documentation/perf-list.txt

1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
11 'perf list' [--no-desc] [--long-desc]
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
28 -v::
29 --long-desc::
32 --debug::
35 --details::
39 --deprecated::
42 --unit::
44 (e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom)
46 -j::
47 --json::
50 -o::
51 --output=::
56 ---------------
62  u - user-space counting
63  k - kernel counting
64  h - hypervisor counting
65  I - non idle counting
66  G - guest counting (in KVM guests)
67  H - host counting (not in KVM guests)
68  p - precise level
69  P - use maximum detected precise level
70  S - read sample value (PERF_SAMPLE_READ)
71  D - pin the event to the PMU
72  W - group is weak and will fallback to non-group if not schedulable,
73  e - group or event are exclusive and do not share the PMU
76 address should be. The 'p' modifier can be specified multiple times:
78  0 - SAMPLE_IP can have arbitrary skid
79  1 - SAMPLE_IP must have constant skid
80  2 - SAMPLE_IP requested to have 0 skid
81  3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
85 which supports up to precise-level 2, and precise level 3 for
88 On AMD systems it is implemented using IBS OP (up to precise-level 2).
90 inherently non-precise and IBS is inherently precise. (i.e. ibs_op//,
92 works with event types 0x76 (cpu-cycles, CPU clocks not halted) and 0xC1
93 (micro-ops retired). Both events map to IBS execution sampling (IBS op)
95 Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS)
99 Manual Volume 2: System Programming, 13.3 Instruction-Based
102  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
103  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
104  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
107 -----------------------------
112 …Lx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Prog…
114 Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the
130   A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
136  perf stat -e r1a8 -a sleep 1
137  perf record -e r1a8 ...
141  perf record -e r1a8 -a sleep 1
142  perf record -e cpu/r1a8/ ...
143  perf record -e cpu/r0x1a8/ ...
158   28FH     03H  op_cache_hit_miss.op_cache_hit  Counts Op Cache micro-tag
162 EventSelect bits have to be specified via bits 32-35 as can be seen with:
168  perf stat -e r20000038f -a sleep 1
169  perf record -e r20000038f ...
173  perf record -e r20000038f -a sleep 1
174  perf record -e cpu/r20000038f/ ...
175  perf record -e cpu/r0x20000038f/ ...
181 --------------
192 be specified as
194   perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
198   perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
201 ---------------
205 with perf stat -a. They can be bound to one logical CPU, but will measure
211   perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
220   perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
221   perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
225   perf stat -I 1000 -e power/energy-cores/  -a
228 -------------------
230 For non root users generally only context switched PMU events are available.
238 sysctl to -1, which allows non root to use these events.
245 -------
249 intel-pt.txt document.
252 --------------------
254 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
262   perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
273   perf stat -e cpu/event=0,umask=0x3,percore=1/
277 ------------
286 errors. Event groups can be specified using { }.
288   perf stat -e '{instructions,cycles}' ...
294 ref-cycles. Some special events have restrictions on which counter they
296 When too many events are specified in the group some of them will not
309 ---------------
313   perf record -e '{cycles,instructions}:S' ...
314   perf report --group
324 -------
330 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
334 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
354 types specified.
358 . '--raw-dump', shows the raw-dump of all the events.
359 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
363 --------
364 linkperf:perf-stat[1], linkperf:perf-top[1],
365 linkperf:perf-record[1],
366 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: …