include/asm/cpufeatures.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS			21	   /* N 32-bit words worth of info */
17 #define NBUGINTS			2	   /* N 32-bit bug flags */
20  * Note: If the comment begins with a quoted string, that string is used
25  * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
32 #define X86_FEATURE_PSE			( 0*32+ 3) /* Page Size Extensions */
34 #define X86_FEATURE_MSR			( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36		( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT			( 0*32+28) /* Hyper-Threading */
57 #define X86_FEATURE_IA64		( 0*32+30) /* IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM			( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
70 #define X86_FEATURE_3DNOWEXT		( 1*32+30) /* AMD 3DNow extensions */
71 #define X86_FEATURE_3DNOW		( 1*32+31) /* 3DNow */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
76 #define X86_FEATURE_LRTI		( 2*32+ 3) /* LongRun table interface */
78 /* Other features, Linux-defined mapping, word 3 */
80 #define X86_FEATURE_CXMMX		( 3*32+ 0) /* Cyrix MMX extensions */
81 #define X86_FEATURE_K6_MTRR		( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
82 #define X86_FEATURE_CYRIX_ARR		( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
83 #define X86_FEATURE_CENTAUR_MCR		( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
86 #define X86_FEATURE_K8			( 3*32+ 4) /* "" Opteron, Athlon64 */
87 /* FREE, was #define X86_FEATURE_K7			( 3*32+ 5) "" Athlon */
88 #define X86_FEATURE_P3			( 3*32+ 6) /* "" P3 */
89 #define X86_FEATURE_P4			( 3*32+ 7) /* "" P4 */
90 #define X86_FEATURE_CONSTANT_TSC	( 3*32+ 8) /* TSC ticks at a constant rate */
91 #define X86_FEATURE_UP			( 3*32+ 9) /* SMP kernel running on UP */
92 #define X86_FEATURE_ART			( 3*32+10) /* Always running timer (ART) */
93 #define X86_FEATURE_ARCH_PERFMON	( 3*32+11) /* Intel Architectural PerfMon */
94 #define X86_FEATURE_PEBS		( 3*32+12) /* Precise-Event Based Sampling */
95 #define X86_FEATURE_BTS			( 3*32+13) /* Branch Trace Store */
96 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
97 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
98 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
99 #define X86_FEATURE_AMD_LBR_V2		( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
100 /* FREE, was #define X86_FEATURE_LFENCE_RDTSC		( 3*32+18) "" LFENCE synchronizes RDTSC */
101 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
102 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
103 #define X86_FEATURE_ALWAYS		( 3*32+21) /* "" Always-present feature */
104 #define X86_FEATURE_XTOPOLOGY		( 3*32+22) /* CPU topology enum extensions */
105 #define X86_FEATURE_TSC_RELIABLE	( 3*32+23) /* TSC is known to be reliable */
106 #define X86_FEATURE_NONSTOP_TSC		( 3*32+24) /* TSC does not stop in C states */
107 #define X86_FEATURE_CPUID		( 3*32+25) /* CPU has CPUID instruction itself */
108 #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
109 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
110 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (AP…
111 #define X86_FEATURE_RAPL		( 3*32+29) /* AMD/Hygon RAPL interface */
112 #define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */
113 #define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3		( 4*32+ 0) /* "pni" SSE-3 */
118 #define X86_FEATURE_DTES64		( 4*32+ 2) /* 64-bit Debug Store */
119 #define X86_FEATURE_MWAIT		( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */
120 #define X86_FEATURE_DSCPL		( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
125 #define X86_FEATURE_SSSE3		( 4*32+ 9) /* Supplemental SSE-3 */
128 #define X86_FEATURE_FMA			( 4*32+12) /* Fused multiply-add */
134 #define X86_FEATURE_XMM4_1		( 4*32+19) /* "sse4_1" SSE-4.1 */
135 #define X86_FEATURE_XMM4_2		( 4*32+20) /* "sse4_2" SSE-4.2 */
144 #define X86_FEATURE_F16C		( 4*32+29) /* 16-bit FP conversions */
146 #define X86_FEATURE_HYPERVISOR		( 4*32+31) /* Running on a hypervisor */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
150 #define X86_FEATURE_XSTORE_EN		( 5*32+ 3) /* "rng_en" RNG enabled */
151 #define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
152 #define X86_FEATURE_XCRYPT_EN		( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
164 #define X86_FEATURE_EXTAPIC		( 6*32+ 3) /* Extended APIC space */
165 #define X86_FEATURE_CR8_LEGACY		( 6*32+ 4) /* CR8 in 32-bit mode */
167 #define X86_FEATURE_SSE4A		( 6*32+ 6) /* SSE-4A */
169 #define X86_FEATURE_3DNOWPREFETCH	( 6*32+ 8) /* 3DNow prefetch instructions */
184 #define X86_FEATURE_PTSC		( 6*32+27) /* Performance time-stamp counter */
189  * Auxiliary flags: Linux defined - For features scattered in various
194 #define X86_FEATURE_RING3MWAIT		( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */
197 #define X86_FEATURE_EPB			( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
201 #define X86_FEATURE_TDX_HOST_PLATFORM	( 7*32+ 7) /* Platform supports being a TDX host */
202 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
207 #define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
231 #define X86_FEATURE_VPID		( 8*32+ 3) /* Intel Virtual Processor ID */
235 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
242 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
246 #define X86_FEATURE_BMI1		( 9*32+ 3) /* 1st group bit manipulation extensions */
259 #define X86_FEATURE_AVX512F		( 9*32+16) /* AVX-512 Foundation */
260 #define X86_FEATURE_AVX512DQ		( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
264 #define X86_FEATURE_AVX512IFMA		( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
268 #define X86_FEATURE_AVX512PF		( 9*32+26) /* AVX-512 Prefetch */
269 #define X86_FEATURE_AVX512ER		( 9*32+27) /* AVX-512 Exponential and Reciprocal */
270 #define X86_FEATURE_AVX512CD		( 9*32+28) /* AVX-512 Conflict Detection */
272 #define X86_FEATURE_AVX512BW		( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
273 #define X86_FEATURE_AVX512VL		( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
279 #define X86_FEATURE_XSAVES		(10*32+ 3) /* XSAVES/XRSTORS instructions */
283  * Extended auxiliary flags: Linux defined - for features scattered in various
291 #define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */
295 #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
321 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
326 #define X86_FEATURE_FZRM		(12*32+10) /* "" Fast zero-length REP MOVSB */
334 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
343 …MD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
359 #define X86_FEATURE_HWP			(14*32+ 7) /* Intel Hardware P-states */
370 #define X86_FEATURE_NRIPS		(15*32+ 3) /* "nrip_save" SVM next_rip save */
373 #define X86_FEATURE_FLUSHBYASID		(15*32+ 6) /* flush-by-ASID support */
385 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
388 #define X86_FEATURE_PKU			(16*32+ 3) /* Protection Keys for Userspace */
395 #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
397 #define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instruct…
400 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
409 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
412 #define X86_FEATURE_SMCA		(17*32+ 3) /* Scalable MCA */
414 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
415 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
416 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
418 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
440 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
444 #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
446 #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
447 #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* AMD SEV-ES full debug state swap support */
449 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
451 #define X86_FEATURE_WRMSR_XX_BASE_NS	(20*32+ 1) /* "" WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serial…
469 #define X86_BUG_AMD_TLB_MMATCH		X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
477  * 64-bit kernels don't use X86_BUG_ESPFIX.  Make the define conditional
480 #define X86_BUG_ESPFIX			X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
482 #define X86_BUG_NULL_SEG		X86_BUG(10) /* Nulling a selector preserves the base */
501 #define X86_BUG_SMT_RSB			X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictio…
503 #define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* CPU may incur #MC if non-TD software does partial write …