Lines Matching +full:0 +full:x12c

16 #define TEGRA210_MVC_RX_STATUS			0x0c
17 #define TEGRA210_MVC_RX_INT_STATUS		0x10
18 #define TEGRA210_MVC_RX_INT_MASK		0x14
19 #define TEGRA210_MVC_RX_INT_SET			0x18
20 #define TEGRA210_MVC_RX_INT_CLEAR		0x1c
21 #define TEGRA210_MVC_RX_CIF_CTRL		0x20
27 #define TEGRA210_MVC_TX_STATUS			0x4c
28 #define TEGRA210_MVC_TX_INT_STATUS		0x50
29 #define TEGRA210_MVC_TX_INT_MASK		0x54
30 #define TEGRA210_MVC_TX_INT_SET			0x58
31 #define TEGRA210_MVC_TX_INT_CLEAR		0x5c
32 #define TEGRA210_MVC_TX_CIF_CTRL		0x60
35 #define TEGRA210_MVC_ENABLE			0x80
36 #define TEGRA210_MVC_SOFT_RESET			0x84
37 #define TEGRA210_MVC_CG				0x88
38 #define TEGRA210_MVC_STATUS			0x90
39 #define TEGRA210_MVC_INT_STATUS			0x94
40 #define TEGRA210_MVC_CTRL			0xa8
41 #define TEGRA210_MVC_SWITCH			0xac
42 #define TEGRA210_MVC_INIT_VOL			0xb0
43 #define TEGRA210_MVC_TARGET_VOL			0xd0
44 #define TEGRA210_MVC_DURATION			0xf0
45 #define TEGRA210_MVC_DURATION_INV		0xf4
46 #define TEGRA210_MVC_POLY_N1			0xf8
47 #define TEGRA210_MVC_POLY_N2			0xfc
48 #define TEGRA210_MVC_PEAK_CTRL			0x100
49 #define TEGRA210_MVC_CFG_RAM_CTRL		0x104
50 #define TEGRA210_MVC_CFG_RAM_DATA		0x108
51 #define TEGRA210_MVC_PEAK_VALUE			0x10c
52 #define TEGRA210_MVC_CONFIG_ERR_TYPE		0x12c
55 #define TEGRA210_MVC_EN_SHIFT			0
59 #define TEGRA210_MUTE_MASK_EN			0xff
74 #define TEGRA210_MVC_CTRL_DEFAULT	0x40000003
76 #define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY	0x01000000
77 #define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR	0x00000000
89 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT		0
90 #define TEGRA210_MVC_CFG_RAM_CTRL_ADDR_MASK		(0x1ff << TEGRA210_MVC_CFG_RAM_CTRL_ADDR_SHIFT)