31  * successful first boot. Hence core 0 will be running and other cores
39 	skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING;  in skl_dsp_init_core_state()
40 	skl->cores.usage_count[SKL_DSP_CORE0_ID] = 1;  in skl_dsp_init_core_state()
42 	for (i = SKL_DSP_CORE0_ID + 1; i < skl->cores.count; i++) {  in skl_dsp_init_core_state()
43 		skl->cores.state[i] = SKL_DSP_RESET;  in skl_dsp_init_core_state()
44 		skl->cores.usage_count[i] = 0;  in skl_dsp_init_core_state()
48 /* Get the mask for all enabled cores */
55 	core_mask = SKL_DSP_CORES_MASK(skl->cores.count);  in skl_dsp_get_enabled_cores()
59 	/* Cores having CPA bit set */  in skl_dsp_get_enabled_cores()
63 	/* And cores having CRST bit cleared */  in skl_dsp_get_enabled_cores()
67 	/* And cores having CSTALL bit cleared */  in skl_dsp_get_enabled_cores()
72 	dev_dbg(ctx->dev, "DSP enabled cores mask = %x\n", en_cores_mask);  in skl_dsp_get_enabled_cores()
341 	if (core_id >= skl->cores.count) {  in skl_dsp_get_core()
346 	skl->cores.usage_count[core_id]++;  in skl_dsp_get_core()
348 	if (skl->cores.state[core_id] == SKL_DSP_RESET) {  in skl_dsp_get_core()
358 			core_id, skl->cores.state[core_id],  in skl_dsp_get_core()
359 			skl->cores.usage_count[core_id]);  in skl_dsp_get_core()
370 	if (core_id >= skl->cores.count) {  in skl_dsp_put_core()
375 	if ((--skl->cores.usage_count[core_id] == 0) &&  in skl_dsp_put_core()
376 		(skl->cores.state[core_id] != SKL_DSP_RESET)) {  in skl_dsp_put_core()
381 			skl->cores.usage_count[core_id]++;  in skl_dsp_put_core()
386 			core_id, skl->cores.state[core_id],  in skl_dsp_put_core()
387 			skl->cores.usage_count[core_id]);  in skl_dsp_put_core()