Lines Matching +full:vf610 +full:- +full:sai +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
50 * @sai: SAI context
53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) in fsl_sai_dir_is_synced() argument
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) in fsl_sai_get_pins_state() argument
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); in fsl_sai_get_pins_state()
81 state = pinctrl_lookup_state(sai->pinctrl, "default"); in fsl_sai_get_pins_state()
88 struct fsl_sai *sai = (struct fsl_sai *)devid; in fsl_sai_isr() local
89 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
90 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); in fsl_sai_isr()
160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); in fsl_sai_isr()
169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_set_dai_tdm_slot() local
171 sai->slots = slots; in fsl_sai_set_dai_tdm_slot()
172 sai->slot_width = slot_width; in fsl_sai_set_dai_tdm_slot()
180 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); in fsl_sai_set_dai_bclk_ratio() local
182 sai->bclk_ratio = ratio; in fsl_sai_set_dai_bclk_ratio()
190 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_set_dai_sysclk_tr() local
191 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_sysclk_tr()
208 return -EINVAL; in fsl_sai_set_dai_sysclk_tr()
211 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_sysclk_tr()
219 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); in fsl_sai_set_mclk_rate() local
222 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], in fsl_sai_set_mclk_rate()
223 sai->pll8k_clk, sai->pll11k_clk, freq); in fsl_sai_set_mclk_rate()
225 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); in fsl_sai_set_mclk_rate()
227 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); in fsl_sai_set_mclk_rate()
235 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_set_dai_sysclk() local
243 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); in fsl_sai_set_dai_sysclk()
244 return -EINVAL; in fsl_sai_set_dai_sysclk()
247 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { in fsl_sai_set_dai_sysclk()
248 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); in fsl_sai_set_dai_sysclk()
249 return -EINVAL; in fsl_sai_set_dai_sysclk()
252 if (sai->mclk_streams == 0) { in fsl_sai_set_dai_sysclk()
261 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
267 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
275 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_set_dai_fmt_tr() local
276 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_fmt_tr()
279 if (!sai->is_lsb_first) in fsl_sai_set_dai_fmt_tr()
282 sai->is_pdm_mode = false; in fsl_sai_set_dai_fmt_tr()
283 sai->is_dsp_mode = false; in fsl_sai_set_dai_fmt_tr()
289 * frame sync starts one serial clock cycle earlier, in fsl_sai_set_dai_fmt_tr()
306 * frame sync starts one serial clock cycle earlier, in fsl_sai_set_dai_fmt_tr()
312 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
320 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
325 sai->is_pdm_mode = true; in fsl_sai_set_dai_fmt_tr()
330 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
333 /* DAI clock inversion */ in fsl_sai_set_dai_fmt_tr()
341 /* Invert bit clock */ in fsl_sai_set_dai_fmt_tr()
345 /* Invert frame clock */ in fsl_sai_set_dai_fmt_tr()
352 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
355 /* DAI clock provider masks */ in fsl_sai_set_dai_fmt_tr()
360 sai->is_consumer_mode = false; in fsl_sai_set_dai_fmt_tr()
363 sai->is_consumer_mode = true; in fsl_sai_set_dai_fmt_tr()
367 sai->is_consumer_mode = false; in fsl_sai_set_dai_fmt_tr()
371 sai->is_consumer_mode = true; in fsl_sai_set_dai_fmt_tr()
374 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_fmt_tr()
379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_set_dai_fmt_tr()
392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); in fsl_sai_set_dai_fmt()
398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); in fsl_sai_set_dai_fmt()
405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); in fsl_sai_set_bclk() local
406 unsigned int reg, ofs = sai->soc_data->reg_offset; in fsl_sai_set_bclk()
412 bool support_1_1_ratio = sai->verid.version >= 0x0301; in fsl_sai_set_bclk()
415 if (sai->is_consumer_mode) in fsl_sai_set_bclk()
423 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; in fsl_sai_set_bclk()
428 clk_rate = clk_get_rate(sai->mclk_clk[id]); in fsl_sai_set_bclk()
440 diff = abs((long)clk_rate - ratio * freq); in fsl_sai_set_bclk()
449 dev_dbg(dai->dev, in fsl_sai_set_bclk()
450 "ratio %d for freq %dHz based on clock %ldHz\n", in fsl_sai_set_bclk()
456 sai->mclk_id[tx] = id; in fsl_sai_set_bclk()
465 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", in fsl_sai_set_bclk()
467 return -EINVAL; in fsl_sai_set_bclk()
470 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", in fsl_sai_set_bclk()
471 sai->mclk_id[tx], savediv, bestdiff); in fsl_sai_set_bclk()
476 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback in fsl_sai_set_bclk()
478 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback in fsl_sai_set_bclk()
480 * 4) For Tx and Rx are both Synchronous with another SAI, we just in fsl_sai_set_bclk()
483 if (fsl_sai_dir_is_synced(sai, adir)) in fsl_sai_set_bclk()
485 else if (!sai->synchronous[dir]) in fsl_sai_set_bclk()
490 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, in fsl_sai_set_bclk()
491 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
494 regmap_update_bits(sai->regmap, reg, in fsl_sai_set_bclk()
497 if (fsl_sai_dir_is_synced(sai, adir)) in fsl_sai_set_bclk()
498 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
501 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
504 regmap_update_bits(sai->regmap, reg, in fsl_sai_set_bclk()
506 savediv / 2 - 1); in fsl_sai_set_bclk()
516 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_hw_params() local
517 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_params()
518 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_params()
521 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; in fsl_sai_hw_params()
524 int dl_cfg_cnt = sai->dl_cfg_cnt; in fsl_sai_hw_params()
534 if (sai->slot_width) in fsl_sai_hw_params()
535 slot_width = sai->slot_width; in fsl_sai_hw_params()
537 if (sai->slots) in fsl_sai_hw_params()
538 slots = sai->slots; in fsl_sai_hw_params()
539 else if (sai->bclk_ratio) in fsl_sai_hw_params()
540 slots = sai->bclk_ratio / slot_width; in fsl_sai_hw_params()
548 if (sai->is_pdm_mode) { in fsl_sai_hw_params()
561 dev_err(cpu_dai->dev, "channel not supported\n"); in fsl_sai_hw_params()
562 return -EINVAL; in fsl_sai_hw_params()
565 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); in fsl_sai_hw_params()
567 if (!IS_ERR_OR_NULL(sai->pinctrl)) { in fsl_sai_hw_params()
568 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); in fsl_sai_hw_params()
569 if (!IS_ERR_OR_NULL(sai->pins_state)) { in fsl_sai_hw_params()
570 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); in fsl_sai_hw_params()
572 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); in fsl_sai_hw_params()
578 if (!sai->is_consumer_mode) { in fsl_sai_hw_params()
583 /* Do not enable the clock if it is already enabled */ in fsl_sai_hw_params()
584 if (!(sai->mclk_streams & BIT(substream->stream))) { in fsl_sai_hw_params()
585 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_params()
589 sai->mclk_streams |= BIT(substream->stream); in fsl_sai_hw_params()
593 if (!sai->is_dsp_mode && !sai->is_pdm_mode) in fsl_sai_hw_params()
599 if (sai->is_lsb_first || sai->is_pdm_mode) in fsl_sai_hw_params()
602 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); in fsl_sai_hw_params()
606 /* Set to output mode to avoid tri-stated data pins */ in fsl_sai_hw_params()
611 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will in fsl_sai_hw_params()
612 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), in fsl_sai_hw_params()
616 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { in fsl_sai_hw_params()
617 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), in fsl_sai_hw_params()
621 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), in fsl_sai_hw_params()
628 * - Can't used for singel dataline/FIFO case except the FIFO0 in fsl_sai_hw_params()
629 * - Can't used for multi dataline/FIFO case except the enabled FIFOs in fsl_sai_hw_params()
634 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) in fsl_sai_hw_params()
635 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
638 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
641 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; in fsl_sai_hw_params()
642 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + in fsl_sai_hw_params()
645 if (sai->is_multi_fifo_dma) { in fsl_sai_hw_params()
646 sai->audio_config[tx].words_per_fifo = min(slots, channels); in fsl_sai_hw_params()
648 sai->audio_config[tx].n_fifos_dst = pins; in fsl_sai_hw_params()
649 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; in fsl_sai_hw_params()
651 sai->audio_config[tx].n_fifos_src = pins; in fsl_sai_hw_params()
652 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; in fsl_sai_hw_params()
654 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; in fsl_sai_hw_params()
655 dma_params->peripheral_config = &sai->audio_config[tx]; in fsl_sai_hw_params()
656 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); in fsl_sai_hw_params()
658 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : in fsl_sai_hw_params()
659 (dma_params->maxburst - 1); in fsl_sai_hw_params()
660 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), in fsl_sai_hw_params()
661 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_hw_params()
666 for (i = 0; i < sai->soc_data->pins; i++) { in fsl_sai_hw_params()
667 trce_mask = (1 << (i + 1)) - 1; in fsl_sai_hw_params()
672 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_params()
678 * There will be no frame sync clock issue, because word width impact in fsl_sai_hw_params()
679 * the generation of frame sync clock. in fsl_sai_hw_params()
685 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && in fsl_sai_hw_params()
686 !sai->is_consumer_mode) in fsl_sai_hw_params()
687 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
690 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
694 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), in fsl_sai_hw_params()
699 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && in fsl_sai_hw_params()
700 !sai->is_consumer_mode) in fsl_sai_hw_params()
701 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
704 regmap_write(sai->regmap, FSL_SAI_xMR(tx), in fsl_sai_hw_params()
705 ~0UL - ((1 << min(channels, slots)) - 1)); in fsl_sai_hw_params()
713 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_hw_free() local
714 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_free()
715 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_free()
718 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); in fsl_sai_hw_free()
720 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_free()
723 if (!sai->is_consumer_mode && in fsl_sai_hw_free()
724 sai->mclk_streams & BIT(substream->stream)) { in fsl_sai_hw_free()
725 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_free()
726 sai->mclk_streams &= ~BIT(substream->stream); in fsl_sai_hw_free()
732 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) in fsl_sai_config_disable() argument
734 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_config_disable()
738 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) in fsl_sai_config_disable()
743 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
749 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); in fsl_sai_config_disable()
750 } while (--count && xcsr & FSL_SAI_CSR_TERE); in fsl_sai_config_disable()
752 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
756 * For sai master mode, after several open/close sai, in fsl_sai_config_disable()
757 * there will be no frame clock, and can't recover in fsl_sai_config_disable()
760 * next sai version. in fsl_sai_config_disable()
762 if (!sai->is_consumer_mode) { in fsl_sai_config_disable()
764 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); in fsl_sai_config_disable()
766 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); in fsl_sai_config_disable()
773 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_trigger() local
774 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_trigger()
776 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_trigger()
786 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
787 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
788 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
789 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
799 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
802 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
815 if (fsl_sai_dir_is_synced(sai, adir)) in fsl_sai_trigger()
816 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), in fsl_sai_trigger()
819 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
825 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
827 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
831 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); in fsl_sai_trigger()
837 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) in fsl_sai_trigger()
838 fsl_sai_config_disable(sai, adir); in fsl_sai_trigger()
846 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) in fsl_sai_trigger()
847 fsl_sai_config_disable(sai, dir); in fsl_sai_trigger()
851 return -EINVAL; in fsl_sai_trigger()
860 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); in fsl_sai_startup() local
861 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_startup()
868 if (sai->soc_data->use_edma) in fsl_sai_startup()
869 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_sai_startup()
871 tx ? sai->dma_params_tx.maxburst : in fsl_sai_startup()
872 sai->dma_params_rx.maxburst); in fsl_sai_startup()
874 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_sai_startup()
882 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); in fsl_sai_dai_probe() local
883 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_dai_probe()
886 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
887 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
889 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_dai_probe()
890 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_dai_probe()
892 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), in fsl_sai_dai_probe()
893 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
894 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); in fsl_sai_dai_probe()
895 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), in fsl_sai_dai_probe()
896 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
897 sai->dma_params_rx.maxburst - 1); in fsl_sai_dai_probe()
899 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, in fsl_sai_dai_probe()
900 &sai->dma_params_rx); in fsl_sai_dai_probe()
919 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); in fsl_sai_dai_resume() local
920 struct device *dev = &sai->pdev->dev; in fsl_sai_dai_resume()
923 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { in fsl_sai_dai_resume()
924 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); in fsl_sai_dai_resume()
936 .stream_name = "CPU-Playback",
945 .stream_name = "CPU-Capture",
957 .name = "fsl-sai",
1012 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_readable_reg() local
1013 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_readable_reg()
1068 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_volatile_reg() local
1069 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_volatile_reg()
1111 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_writeable_reg() local
1112 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_writeable_reg()
1158 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_check_version() local
1159 unsigned char ofs = sai->soc_data->reg_offset; in fsl_sai_check_version()
1166 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); in fsl_sai_check_version()
1172 sai->verid.version = val & in fsl_sai_check_version()
1174 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; in fsl_sai_check_version()
1175 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; in fsl_sai_check_version()
1177 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); in fsl_sai_check_version()
1184 sai->param.slot_num = 1 << in fsl_sai_check_version()
1188 sai->param.fifo_depth = 1 << in fsl_sai_check_version()
1192 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; in fsl_sai_check_version()
1207 offset = nbidx - fbidx - 1; in fsl_sai_calc_dl_off()
1209 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); in fsl_sai_calc_dl_off()
1224 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) in fsl_sai_read_dlcfg() argument
1226 struct platform_device *pdev = sai->pdev; in fsl_sai_read_dlcfg()
1227 struct device_node *np = pdev->dev.of_node; in fsl_sai_read_dlcfg()
1228 struct device *dev = &pdev->dev; in fsl_sai_read_dlcfg()
1242 return -EINVAL; in fsl_sai_read_dlcfg()
1247 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); in fsl_sai_read_dlcfg()
1249 return -ENOMEM; in fsl_sai_read_dlcfg()
1252 soc_dl = BIT(sai->soc_data->pins) - 1; in fsl_sai_read_dlcfg()
1254 cfg[0].pins[0] = sai->soc_data->pins; in fsl_sai_read_dlcfg()
1259 cfg[0].pins[1] = sai->soc_data->pins; in fsl_sai_read_dlcfg()
1272 return -EINVAL; in fsl_sai_read_dlcfg()
1276 return -EINVAL; in fsl_sai_read_dlcfg()
1280 return -EINVAL; in fsl_sai_read_dlcfg()
1284 return -EINVAL; in fsl_sai_read_dlcfg()
1304 sai->dl_cfg = cfg; in fsl_sai_read_dlcfg()
1305 sai->dl_cfg_cnt = num_cfg + 1; in fsl_sai_read_dlcfg()
1314 struct device_node *np = pdev->dev.of_node; in fsl_sai_probe()
1315 struct device *dev = &pdev->dev; in fsl_sai_probe()
1316 struct fsl_sai *sai; in fsl_sai_probe() local
1324 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); in fsl_sai_probe()
1325 if (!sai) in fsl_sai_probe()
1326 return -ENOMEM; in fsl_sai_probe()
1328 sai->pdev = pdev; in fsl_sai_probe()
1329 sai->soc_data = of_device_get_match_data(dev); in fsl_sai_probe()
1331 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); in fsl_sai_probe()
1333 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); in fsl_sai_probe()
1337 if (sai->soc_data->reg_offset == 8) { in fsl_sai_probe()
1344 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); in fsl_sai_probe()
1345 if (IS_ERR(sai->regmap)) { in fsl_sai_probe()
1347 return PTR_ERR(sai->regmap); in fsl_sai_probe()
1350 sai->bus_clk = devm_clk_get(dev, "bus"); in fsl_sai_probe()
1352 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) in fsl_sai_probe()
1353 sai->bus_clk = devm_clk_get(dev, "sai"); in fsl_sai_probe()
1354 if (IS_ERR(sai->bus_clk)) { in fsl_sai_probe()
1355 dev_err(dev, "failed to get bus clock: %ld\n", in fsl_sai_probe()
1356 PTR_ERR(sai->bus_clk)); in fsl_sai_probe()
1357 /* -EPROBE_DEFER */ in fsl_sai_probe()
1358 return PTR_ERR(sai->bus_clk); in fsl_sai_probe()
1363 sai->mclk_clk[i] = devm_clk_get(dev, tmp); in fsl_sai_probe()
1364 if (IS_ERR(sai->mclk_clk[i])) { in fsl_sai_probe()
1365 dev_err(dev, "failed to get mclk%d clock: %ld\n", in fsl_sai_probe()
1366 i, PTR_ERR(sai->mclk_clk[i])); in fsl_sai_probe()
1367 sai->mclk_clk[i] = NULL; in fsl_sai_probe()
1371 if (sai->soc_data->mclk0_is_mclk1) in fsl_sai_probe()
1372 sai->mclk_clk[0] = sai->mclk_clk[1]; in fsl_sai_probe()
1374 sai->mclk_clk[0] = sai->bus_clk; in fsl_sai_probe()
1376 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, in fsl_sai_probe()
1377 &sai->pll11k_clk); in fsl_sai_probe()
1381 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) in fsl_sai_probe()
1382 sai->is_multi_fifo_dma = true; in fsl_sai_probe()
1385 ret = fsl_sai_read_dlcfg(sai); in fsl_sai_probe()
1396 np->name, sai); in fsl_sai_probe()
1402 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, in fsl_sai_probe()
1406 sai->synchronous[RX] = true; in fsl_sai_probe()
1407 sai->synchronous[TX] = false; in fsl_sai_probe()
1408 sai->cpu_dai_drv.symmetric_rate = 1; in fsl_sai_probe()
1409 sai->cpu_dai_drv.symmetric_channels = 1; in fsl_sai_probe()
1410 sai->cpu_dai_drv.symmetric_sample_bits = 1; in fsl_sai_probe()
1412 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && in fsl_sai_probe()
1413 of_property_read_bool(np, "fsl,sai-asynchronous")) { in fsl_sai_probe()
1416 return -EINVAL; in fsl_sai_probe()
1419 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { in fsl_sai_probe()
1421 sai->synchronous[RX] = false; in fsl_sai_probe()
1422 sai->synchronous[TX] = true; in fsl_sai_probe()
1423 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { in fsl_sai_probe()
1425 sai->synchronous[RX] = false; in fsl_sai_probe()
1426 sai->synchronous[TX] = false; in fsl_sai_probe()
1427 sai->cpu_dai_drv.symmetric_rate = 0; in fsl_sai_probe()
1428 sai->cpu_dai_drv.symmetric_channels = 0; in fsl_sai_probe()
1429 sai->cpu_dai_drv.symmetric_sample_bits = 0; in fsl_sai_probe()
1432 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); in fsl_sai_probe()
1434 if (sai->mclk_direction_output && in fsl_sai_probe()
1435 of_device_is_compatible(np, "fsl,imx6ul-sai")) { in fsl_sai_probe()
1436 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); in fsl_sai_probe()
1442 index = of_alias_get_id(np, "sai"); in fsl_sai_probe()
1450 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; in fsl_sai_probe()
1451 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; in fsl_sai_probe()
1452 sai->dma_params_rx.maxburst = in fsl_sai_probe()
1453 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; in fsl_sai_probe()
1454 sai->dma_params_tx.maxburst = in fsl_sai_probe()
1455 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; in fsl_sai_probe()
1457 sai->pinctrl = devm_pinctrl_get(&pdev->dev); in fsl_sai_probe()
1459 platform_set_drvdata(pdev, sai); in fsl_sai_probe()
1471 /* Get sai version */ in fsl_sai_probe()
1474 dev_warn(dev, "Error reading SAI version: %d\n", ret); in fsl_sai_probe()
1477 if (sai->mclk_direction_output && in fsl_sai_probe()
1478 sai->soc_data->max_register >= FSL_SAI_MCTL) { in fsl_sai_probe()
1479 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, in fsl_sai_probe()
1484 if (ret < 0 && ret != -ENOSYS) in fsl_sai_probe()
1491 if (sai->soc_data->use_imx_pcm) { in fsl_sai_probe()
1496 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); in fsl_sai_probe()
1508 &sai->cpu_dai_drv, 1); in fsl_sai_probe()
1525 pm_runtime_disable(&pdev->dev); in fsl_sai_remove()
1526 if (!pm_runtime_status_suspended(&pdev->dev)) in fsl_sai_remove()
1527 fsl_sai_runtime_suspend(&pdev->dev); in fsl_sai_remove()
1643 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1644 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1645 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1646 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1647 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1648 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1649 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data },
1650 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data },
1651 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data },
1652 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data },
1653 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data },
1660 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_runtime_suspend() local
1662 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_suspend()
1663 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_suspend()
1665 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_suspend()
1666 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_suspend()
1668 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_suspend()
1670 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) in fsl_sai_runtime_suspend()
1671 cpu_latency_qos_remove_request(&sai->pm_qos_req); in fsl_sai_runtime_suspend()
1673 regcache_cache_only(sai->regmap, true); in fsl_sai_runtime_suspend()
1680 struct fsl_sai *sai = dev_get_drvdata(dev); in fsl_sai_runtime_resume() local
1681 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_runtime_resume()
1684 ret = clk_prepare_enable(sai->bus_clk); in fsl_sai_runtime_resume()
1686 dev_err(dev, "failed to enable bus clock: %d\n", ret); in fsl_sai_runtime_resume()
1690 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { in fsl_sai_runtime_resume()
1691 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1696 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { in fsl_sai_runtime_resume()
1697 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1702 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) in fsl_sai_runtime_resume()
1703 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); in fsl_sai_runtime_resume()
1705 regcache_cache_only(sai->regmap, false); in fsl_sai_runtime_resume()
1706 regcache_mark_dirty(sai->regmap); in fsl_sai_runtime_resume()
1707 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1708 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1710 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_runtime_resume()
1711 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_runtime_resume()
1713 ret = regcache_sync(sai->regmap); in fsl_sai_runtime_resume()
1717 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) in fsl_sai_runtime_resume()
1718 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), in fsl_sai_runtime_resume()
1724 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_resume()
1725 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1727 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_resume()
1728 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1730 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_resume()
1746 .name = "fsl-sai",
1753 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1755 MODULE_ALIAS("platform:fsl-sai");