1285 	int lrclk, bclk, mask, base;  in wm5100_set_fmt()  local
1290 	bclk = 0;  in wm5100_set_fmt()
1312 		bclk |= WM5100_AIF1_BCLK_MSTR;  in wm5100_set_fmt()
1316 		bclk |= WM5100_AIF1_BCLK_MSTR;  in wm5100_set_fmt()
1328 		bclk |= WM5100_AIF1_BCLK_INV;  in wm5100_set_fmt()
1332 		bclk |= WM5100_AIF1_BCLK_INV;  in wm5100_set_fmt()
1342 			    WM5100_AIF1_BCLK_INV, bclk);  in wm5100_set_fmt()
1405 	int i, base, bclk, aif_rate, lrclk, wl, fl, sr;  in wm5100_hw_params()  local
1421 	/* Target BCLK rate */  in wm5100_hw_params()
1422 	bclk = snd_soc_params_to_bclk(params);  in wm5100_hw_params()
1423 	if (bclk < 0)  in wm5100_hw_params()
1424 		return bclk;  in wm5100_hw_params()
1426 	/* Root for BCLK depends on SYS/ASYNCCLK */  in wm5100_hw_params()
1457 	dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz %s\n",  in wm5100_hw_params()
1458 		bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");  in wm5100_hw_params()
1466 		if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))  in wm5100_hw_params()
1470 			"No valid BCLK for %dHz found from %dHz %s\n",  in wm5100_hw_params()
1471 			bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");  in wm5100_hw_params()
1475 	bclk = i;  in wm5100_hw_params()
1476 	dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);  in wm5100_hw_params()
1477 	snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);  in wm5100_hw_params()
1479 	lrclk = bclk_rates[bclk] / params_rate(params);  in wm5100_hw_params()
1480 	dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);  in wm5100_hw_params()