1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
183 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
184 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
207 	"ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
236 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in adc_power_control()
242 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
244 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
247 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
249 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
258 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in aiftx_power_control()
262 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);  in aiftx_power_control()
263 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);  in aiftx_power_control()
295 	SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
296 	SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
297 	SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
298 	SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
300 	SND_SOC_DAPM_MUX("Digital CH4 Mux",
302 	SND_SOC_DAPM_MUX("Digital CH3 Mux",
304 	SND_SOC_DAPM_MUX("Digital CH2 Mux",
306 	SND_SOC_DAPM_MUX("Digital CH1 Mux",
324 	{"ADC CH1", NULL, "ADC1"},
325 	{"ADC CH2", NULL, "ADC2"},
326 	{"ADC CH3", NULL, "ADC3"},
327 	{"ADC CH4", NULL, "ADC4"},
334 	{"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
335 	{"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
336 	{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
337 	{"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
339 	{"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
340 	{"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
341 	{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
342 	{"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
344 	{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
345 	{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
346 	{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
347 	{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
349 	{"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
350 	{"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
351 	{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
352 	{"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
354 	{"AIFTX", NULL, "Digital CH1 Mux"},
355 	{"AIFTX", NULL, "Digital CH2 Mux"},
356 	{"AIFTX", NULL, "Digital CH3 Mux"},
357 	{"AIFTX", NULL, "Digital CH4 Mux"},
365 	regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);  in nau8540_get_osr()
375 	struct snd_soc_component *component = dai->component;  in nau8540_dai_startup()
380 	if (!osr || !osr->osr)  in nau8540_dai_startup()
381 		return -EINVAL;  in nau8540_dai_startup()
383 	return snd_pcm_hw_constraint_minmax(substream->runtime,  in nau8540_dai_startup()
385 					    0, CLK_ADC_MAX / osr->osr);  in nau8540_dai_startup()
391 	struct snd_soc_component *component = dai->component;  in nau8540_hw_params()
397 	 * ADC clock frequency is defined as Over Sampling Rate (OSR)  in nau8540_hw_params()
403 	if (!osr || !osr->osr)  in nau8540_hw_params()
404 		return -EINVAL;  in nau8540_hw_params()
405 	if (params_rate(params) * osr->osr > CLK_ADC_MAX)  in nau8540_hw_params()
406 		return -EINVAL;  in nau8540_hw_params()
407 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_hw_params()
409 		osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);  in nau8540_hw_params()
425 		return -EINVAL;  in nau8540_hw_params()
428 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_hw_params()
436 	struct snd_soc_component *component = dai->component;  in nau8540_set_fmt()
447 		return -EINVAL;  in nau8540_set_fmt()
457 		return -EINVAL;  in nau8540_set_fmt()
478 		return -EINVAL;  in nau8540_set_fmt()
481 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_set_fmt()
484 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_fmt()
486 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_fmt()
493  * nau8540_set_tdm_slot - configure DAI TX TDM.
507 	struct snd_soc_component *component = dai->component;  in nau8540_set_tdm_slot()
512 		return -EINVAL;  in nau8540_set_tdm_slot()
521 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,  in nau8540_set_tdm_slot()
524 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_tdm_slot()
526 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_tdm_slot()
536 	struct snd_soc_component *component = dai->component;  in nau8540_dai_trigger()
538 	struct regmap *regmap = nau8540->regmap;  in nau8540_dai_trigger()
542 	/* Reading the peak data to detect abnormal data in the ADC channel.  in nau8540_dai_trigger()
544 	 * refresh the ADC channel.  in nau8540_dai_trigger()
554 		dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val);  in nau8540_dai_trigger()
563 			dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val);  in nau8540_dai_trigger()
565 				dev_err(nau8540->dev, "Channel recovery failed!!");  in nau8540_dai_trigger()
566 				ret = -EIO;  in nau8540_dai_trigger()
595 	.name = "nau8540-hifi",
607  * nau8540_calc_fll_param - Calculate FLL parameters.
623 	 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.  in nau8540_calc_fll_param()
632 		return -EINVAL;  in nau8540_calc_fll_param()
633 	fll_param->clk_ref_div = fll_pre_scalar[i].val;  in nau8540_calc_fll_param()
641 		return -EINVAL;  in nau8540_calc_fll_param()
642 	fll_param->ratio = fll_ratio[i].val;  in nau8540_calc_fll_param()
645 	 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be  in nau8540_calc_fll_param()
660 		return -EINVAL;  in nau8540_calc_fll_param()
661 	fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;  in nau8540_calc_fll_param()
663 	/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional  in nau8540_calc_fll_param()
666 	fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);  in nau8540_calc_fll_param()
667 	fll_param->fll_int = (fvco >> 16) & 0x3FF;  in nau8540_calc_fll_param()
668 	fll_param->fll_frac = fvco & 0xFFFF;  in nau8540_calc_fll_param()
677 		NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);  in nau8540_fll_apply()
680 		fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));  in nau8540_fll_apply()
681 	/* FLL 16-bit fractional input */  in nau8540_fll_apply()
682 	regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);  in nau8540_fll_apply()
683 	/* FLL 10-bit integer input */  in nau8540_fll_apply()
685 		NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);  in nau8540_fll_apply()
686 	/* FLL pre-scaler */  in nau8540_fll_apply()
689 		fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);  in nau8540_fll_apply()
694 	if (fll_param->fll_frac) {  in nau8540_fll_apply()
722 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
728 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
735 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
742 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);  in nau8540_set_pll()
743 		return -EINVAL;  in nau8540_set_pll()
745 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_pll()
751 		dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);  in nau8540_set_pll()
754 	dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",  in nau8540_set_pll()
758 	nau8540_fll_apply(nau8540->regmap, &fll_param);  in nau8540_set_pll()
760 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_pll()
774 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
776 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
781 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
783 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
788 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);  in nau8540_set_sysclk()
789 		return -EINVAL;  in nau8540_set_sysclk()
792 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_sysclk()
806 	struct regmap *regmap = nau8540->regmap;  in nau8540_init_regs()
821 	/* ADC OSR selection, CLK_ADC = Fs * OSR;  in nau8540_init_regs()
845 	regcache_cache_only(nau8540->regmap, true);  in nau8540_suspend()
846 	regcache_mark_dirty(nau8540->regmap);  in nau8540_suspend()
855 	regcache_cache_only(nau8540->regmap, false);  in nau8540_resume()
856 	regcache_sync(nau8540->regmap);  in nau8540_resume()
894 	struct device *dev = &i2c->dev;  in nau8540_i2c_probe()
901 			return -ENOMEM;  in nau8540_i2c_probe()
905 	nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);  in nau8540_i2c_probe()
906 	if (IS_ERR(nau8540->regmap))  in nau8540_i2c_probe()
907 		return PTR_ERR(nau8540->regmap);  in nau8540_i2c_probe()
908 	ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);  in nau8540_i2c_probe()
915 	nau8540->dev = dev;  in nau8540_i2c_probe()
916 	nau8540_reset_chip(nau8540->regmap);  in nau8540_i2c_probe()