Lines Matching +full:0 +full:x2500
74 CH_L = 0,
108 return 0; in mt6358_set_mtkaif_protocol()
116 0x01f8, 0x01f8); in playback_gpio_set()
118 0xffff, 0x0249); in playback_gpio_set()
120 0xffff, 0x0249); in playback_gpio_set()
131 0x01f8, 0x01f8); in playback_gpio_reset()
133 0x01f8, 0x0000); in playback_gpio_reset()
135 0xf << 8, 0x0); in playback_gpio_reset()
142 0xffff, 0xffff); in capture_gpio_set()
144 0xffff, 0x0249); in capture_gpio_set()
146 0xffff, 0x0249); in capture_gpio_set()
158 0xffff, 0xffff); in capture_gpio_reset()
160 0xffff, 0x0000); in capture_gpio_reset()
162 0xf << 12, 0x0); in capture_gpio_reset()
169 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6358_set_dcxo()
170 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); in mt6358_set_dcxo()
171 return 0; in mt6358_set_dcxo()
180 0x0); in mt6358_set_clksq()
185 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); in mt6358_set_clksq()
186 return 0; in mt6358_set_clksq()
194 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); in mt6358_set_aud_global_bias()
195 return 0; in mt6358_set_aud_global_bias()
202 0x0066, enable ? 0x0 : 0x66); in mt6358_set_topck()
203 return 0; in mt6358_set_topck()
213 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
217 0xff00, 0x3800); in mt6358_mtkaif_tx_enable()
220 0xff00, 0x3900); in mt6358_mtkaif_tx_enable()
226 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
230 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
237 0xffff, 0x0000); in mt6358_mtkaif_tx_enable()
241 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
244 return 0; in mt6358_mtkaif_tx_enable()
251 0xff00, 0x3000); in mt6358_mtkaif_tx_disable()
252 return 0; in mt6358_mtkaif_tx_disable()
275 return 0; in mt6358_mtkaif_calibration_enable()
286 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
289 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
299 return 0; in mt6358_mtkaif_calibration_disable()
314 return 0; in mt6358_set_mtkaif_calibration_phase()
320 DL_GAIN_8DB = 0,
324 DL_GAIN_N_40DB = 0x1f,
329 #define DL_GAIN_REG_MASK 0x0f9f
333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
342 for (i = 0; i <= target; i++) { in hp_main_output_ramp()
345 0x7 << 8, stage << 8); in hp_main_output_ramp()
347 0x7 << 11, stage << 11); in hp_main_output_ramp()
357 for (i = 0; i <= 0xf; i++) { in hp_aux_feedback_loop_gain_ramp()
358 stage = up ? i : 0xf - i; in hp_aux_feedback_loop_gain_ramp()
360 0xf << 12, stage << 12); in hp_aux_feedback_loop_gain_ramp()
370 for (i = 0x0; i <= 0x6; i++) { in hp_pull_down()
372 0x7, i); in hp_pull_down()
376 for (i = 0x6; i >= 0x1; i--) { in hp_pull_down()
378 0x7, i); in hp_pull_down()
392 int offset = 0, count = 0, reg_idx; in headset_volume_ramp()
406 while (offset >= 0) { in headset_volume_ramp()
432 unsigned int reg = 0; in mt6358_put_volsw()
436 if (ret < 0) in mt6358_put_volsw()
481 0xffff, 0x0000); in mt6358_enable_wov_phase2()
482 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_enable_wov_phase2()
484 0xffff, 0x0800); in mt6358_enable_wov_phase2()
487 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); in mt6358_enable_wov_phase2()
489 0xffff, 0x0025); in mt6358_enable_wov_phase2()
491 0xffff, 0x0005); in mt6358_enable_wov_phase2()
495 0xffff, 0x0000); in mt6358_enable_wov_phase2()
496 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); in mt6358_enable_wov_phase2()
497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); in mt6358_enable_wov_phase2()
498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); in mt6358_enable_wov_phase2()
499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); in mt6358_enable_wov_phase2()
500 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); in mt6358_enable_wov_phase2()
501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); in mt6358_enable_wov_phase2()
502 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); in mt6358_enable_wov_phase2()
504 0xffff, 0x0000); in mt6358_enable_wov_phase2()
506 0xffff, 0x0451); in mt6358_enable_wov_phase2()
507 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); in mt6358_enable_wov_phase2()
509 return 0; in mt6358_enable_wov_phase2()
515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); in mt6358_disable_wov_phase2()
517 0xffff, 0x0450); in mt6358_disable_wov_phase2()
519 0xffff, 0x0c00); in mt6358_disable_wov_phase2()
520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); in mt6358_disable_wov_phase2()
521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); in mt6358_disable_wov_phase2()
522 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); in mt6358_disable_wov_phase2()
523 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); in mt6358_disable_wov_phase2()
524 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); in mt6358_disable_wov_phase2()
525 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); in mt6358_disable_wov_phase2()
526 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); in mt6358_disable_wov_phase2()
528 0xffff, 0x0000); in mt6358_disable_wov_phase2()
532 0xffff, 0x0004); in mt6358_disable_wov_phase2()
534 0xffff, 0x0000); in mt6358_disable_wov_phase2()
535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); in mt6358_disable_wov_phase2()
537 0xffff, 0x0000); in mt6358_disable_wov_phase2()
539 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_disable_wov_phase2()
541 0xffff, 0x0010); in mt6358_disable_wov_phase2()
543 return 0; in mt6358_disable_wov_phase2()
552 ucontrol->value.integer.value[0] = priv->wov_enabled; in mt6358_get_wov()
553 return 0; in mt6358_get_wov()
561 int enabled = ucontrol->value.integer.value[0]; in mt6358_put_wov()
563 if (enabled < 0 || enabled > 1) in mt6358_put_wov()
577 return 0; in mt6358_put_wov()
580 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
581 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
586 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
589 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
592 MT6358_ZCD_CON3, 0, 0x12, 1,
597 8, 4, 0,
600 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
611 0x0, 0x1, 0x2, 0x3,
626 HP_MUX_OPEN = 0,
631 HP_MUX_MASK = 0x7,
652 0,
662 0,
672 RCV_MUX_OPEN = 0,
676 RCV_MUX_MASK = 0x3,
692 0,
706 0x0, 0x1,
732 MIC_TYPE_MUX_IDLE = 0,
738 MIC_TYPE_MUX_MASK = 0x7,
765 0,
775 ADC_MUX_IDLE = 0,
779 ADC_MUX_MASK = 0x3,
795 0,
810 0,
820 PGA_MUX_NONE = 0,
824 PGA_MUX_MASK = 0x3,
840 0,
851 0,
866 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_clksq_event()
873 0x0); in mt_clksq_event()
879 return 0; in mt_clksq_event()
889 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
894 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
896 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
898 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
900 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
903 0xff3f, in mt_sgen_event()
904 0x0000); in mt_sgen_event()
906 0xffff, in mt_sgen_event()
907 0x0001); in mt_sgen_event()
911 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
912 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
918 return 0; in mt_sgen_event()
928 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
936 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
938 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
940 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
942 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_aif_in_event()
946 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_aif_in_event()
947 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_aif_in_event()
955 return 0; in mt_aif_in_event()
964 0x1 << 6, 0x1 << 6); in mtk_hp_enable()
967 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_enable()
973 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_enable()
975 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_enable()
977 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_enable()
979 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_enable()
981 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_enable()
986 0x1055, 0x1055); in mtk_hp_enable()
988 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_enable()
995 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_enable()
998 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1001 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_enable()
1004 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1006 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_enable()
1009 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
1011 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
1013 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
1015 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
1017 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
1019 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
1022 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
1024 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
1028 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_enable()
1031 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
1038 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_enable()
1046 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_enable()
1048 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); in mtk_hp_enable()
1052 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_enable()
1054 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
1056 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
1060 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
1062 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
1067 return 0; in mtk_hp_enable()
1077 0x0f00, 0x0000); in mtk_hp_disable()
1081 0x0001, 0x0000); in mtk_hp_disable()
1085 0x000f, 0x0000); in mtk_hp_disable()
1088 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_disable()
1091 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_disable()
1093 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_disable()
1101 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_disable()
1110 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1113 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_disable()
1116 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_disable()
1120 0x3 << 6, 0x0); in mtk_hp_disable()
1124 0x3 << 4, 0x0); in mtk_hp_disable()
1128 0x3 << 6, 0x0); in mtk_hp_disable()
1131 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mtk_hp_disable()
1135 0x3 << 4, 0x0); in mtk_hp_disable()
1139 0x3 << 2, 0x0); in mtk_hp_disable()
1143 0x1 << 8, 0x1 << 8); in mtk_hp_disable()
1146 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_disable()
1149 0x1055, 0x0); in mtk_hp_disable()
1152 0x1, 0x1); in mtk_hp_disable()
1156 0x1 << 14, 0x0); in mtk_hp_disable()
1160 0x1 << 6, 0x0); in mtk_hp_disable()
1164 return 0; in mtk_hp_disable()
1173 0x1 << 6, 0x1 << 6); in mtk_hp_spk_enable()
1176 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_spk_enable()
1182 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_spk_enable()
1184 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_spk_enable()
1186 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_spk_enable()
1188 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_spk_enable()
1190 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_spk_enable()
1195 0x1055, 0x1055); in mtk_hp_spk_enable()
1197 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_spk_enable()
1204 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_spk_enable()
1207 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1210 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_spk_enable()
1213 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1215 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_spk_enable()
1221 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_spk_enable()
1223 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_spk_enable()
1225 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_spk_enable()
1229 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_spk_enable()
1232 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); in mtk_hp_spk_enable()
1244 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); in mtk_hp_spk_enable()
1246 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); in mtk_hp_spk_enable()
1248 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); in mtk_hp_spk_enable()
1261 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_spk_enable()
1263 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); in mtk_hp_spk_enable()
1265 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); in mtk_hp_spk_enable()
1267 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); in mtk_hp_spk_enable()
1269 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); in mtk_hp_spk_enable()
1271 return 0; in mtk_hp_spk_enable()
1278 0x0f00, 0x0000); in mtk_hp_spk_disable()
1281 0x3 << 2, 0x0000); in mtk_hp_spk_disable()
1285 0x000f, 0x0000); in mtk_hp_spk_disable()
1288 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_spk_disable()
1303 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_spk_disable()
1306 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_spk_disable()
1308 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_spk_disable()
1311 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_spk_disable()
1318 0x3 << 4, 0x0); in mtk_hp_spk_disable()
1321 0x1, 0x0); in mtk_hp_spk_disable()
1325 0x3 << 6, 0x0); in mtk_hp_spk_disable()
1328 0x1 << 1, 0x0); in mtk_hp_spk_disable()
1332 0xff << 8, 0x0000); in mtk_hp_spk_disable()
1336 0x1 << 8, 0x1 << 8); in mtk_hp_spk_disable()
1338 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_spk_disable()
1340 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); in mtk_hp_spk_disable()
1342 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); in mtk_hp_spk_disable()
1346 0x1 << 6, 0x0); in mtk_hp_spk_disable()
1350 return 0; in mtk_hp_spk_disable()
1359 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1362 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1373 else if (priv->dev_counter[device] <= 0) in mt_hp_event()
1374 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", in mt_hp_event()
1387 if (priv->dev_counter[device] > 0) { in mt_hp_event()
1389 } else if (priv->dev_counter[device] < 0) { in mt_hp_event()
1390 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", in mt_hp_event()
1393 priv->dev_counter[device] = 0; in mt_hp_event()
1408 return 0; in mt_hp_event()
1418 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1421 dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1426 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mt_rcv_event()
1429 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mt_rcv_event()
1431 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mt_rcv_event()
1433 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mt_rcv_event()
1435 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mt_rcv_event()
1437 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mt_rcv_event()
1442 0x1055, 0x1055); in mt_rcv_event()
1444 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mt_rcv_event()
1451 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1454 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1456 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mt_rcv_event()
1459 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1461 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1464 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mt_rcv_event()
1467 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mt_rcv_event()
1470 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1472 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1476 0x1, 0x1); in mt_rcv_event()
1479 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1481 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1483 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1493 0x000f, 0x0000); in mt_rcv_event()
1497 0x1, 0x0); in mt_rcv_event()
1504 0x1, 0x0); in mt_rcv_event()
1508 0x1 << 1, 0x0000); in mt_rcv_event()
1512 0xff << 8, 0x0); in mt_rcv_event()
1516 0xff << 8, 0x2 << 8); in mt_rcv_event()
1520 0x1 << 8, 0x1 << 8); in mt_rcv_event()
1524 0x1, 0x0); in mt_rcv_event()
1527 0x1055, 0x0); in mt_rcv_event()
1530 0x1, 0x1); in mt_rcv_event()
1536 return 0; in mt_rcv_event()
1546 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
1560 return 0; in mt_aif_out_event()
1570 dev_dbg(priv->dev, "%s(), event 0x%x\n", in mt_adc_supply_event()
1577 0x1 << 5, 0x1 << 5); in mt_adc_supply_event()
1580 0x0000); in mt_adc_supply_event()
1583 0x2500, 0x0100); in mt_adc_supply_event()
1586 0x2500, 0x2500); in mt_adc_supply_event()
1591 0x2500, 0x0100); in mt_adc_supply_event()
1594 0x2500, 0x0000); in mt_adc_supply_event()
1597 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); in mt_adc_supply_event()
1600 0x1 << 5, 0x0 << 5); in mt_adc_supply_event()
1606 return 0; in mt_adc_supply_event()
1620 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1621 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1622 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_enable()
1623 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); in mt6358_amic_enable()
1624 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); in mt6358_amic_enable()
1627 /* mic bias 0 */ in mt6358_amic_enable()
1633 0xff00, 0x7700); in mt6358_amic_enable()
1637 0xff00, 0x1100); in mt6358_amic_enable()
1641 0xff00, 0x0000); in mt6358_amic_enable()
1646 0xff, 0x21); in mt6358_amic_enable()
1654 MT6358_AUDENC_ANA_CON10, 0x0161); in mt6358_amic_enable()
1657 MT6358_AUDENC_ANA_CON10, 0x0061); in mt6358_amic_enable()
1663 0xf8ff, 0x0004); in mt6358_amic_enable()
1665 0xf8ff, 0x0004); in mt6358_amic_enable()
1669 0xf8ff, 0x0000); in mt6358_amic_enable()
1671 0xf8ff, 0x0000); in mt6358_amic_enable()
1683 0x1 << RG_AUDPREAMPLON_SFT); in mt6358_amic_enable()
1689 0x1 << RG_AUDPREAMPLDCCEN_SFT); in mt6358_amic_enable()
1699 0x1 << RG_AUDADCLPWRUP_SFT); in mt6358_amic_enable()
1711 0x1 << RG_AUDPREAMPRON_SFT); in mt6358_amic_enable()
1717 0x1 << RG_AUDPREAMPRDCCEN_SFT); in mt6358_amic_enable()
1727 0x1 << RG_AUDADCRPWRUP_SFT); in mt6358_amic_enable()
1734 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1737 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1741 0x1 << 12, 0x0); in mt6358_amic_enable()
1748 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); in mt6358_amic_enable()
1751 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); in mt6358_amic_enable()
1753 return 0; in mt6358_amic_enable()
1767 0x0001, 0x0000); in mt6358_amic_disable()
1774 0xf000, 0x0000); in mt6358_amic_disable()
1777 0x1 << 1, 0x0); in mt6358_amic_disable()
1778 /* L preamplifier input sel : off, L PGA 0 dB gain */ in mt6358_amic_disable()
1780 0xfffb, 0x0000); in mt6358_amic_disable()
1784 0x1 << 2, 0x0); in mt6358_amic_disable()
1788 0xf000, 0x0000); in mt6358_amic_disable()
1791 0x1 << 1, 0x0); in mt6358_amic_disable()
1792 /* R preamplifier input sel : off, R PGA 0 dB gain */ in mt6358_amic_disable()
1794 0x0ffb, 0x0000); in mt6358_amic_disable()
1798 0x1 << 2, 0x0); in mt6358_amic_disable()
1802 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_amic_disable()
1806 0x0001, 0x0000); in mt6358_amic_disable()
1810 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_disable()
1812 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1814 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1816 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1826 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); in mt6358_dmic_enable()
1830 0x1 << 12, 0x0); in mt6358_dmic_enable()
1833 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); in mt6358_dmic_enable()
1840 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); in mt6358_dmic_enable()
1842 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); in mt6358_dmic_enable()
1845 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); in mt6358_dmic_enable()
1850 return 0; in mt6358_dmic_enable()
1859 0x0003, 0x0000); in mt6358_dmic_disable()
1865 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); in mt6358_dmic_disable()
1869 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); in mt6358_dmic_disable()
1873 0x1 << 12, 0x0); in mt6358_dmic_disable()
1876 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_dmic_disable()
1900 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_mic_type_event()
1902 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_mic_type_event()
1937 return 0; in mt_mic_type_event()
1946 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_l_event()
1948 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_l_event()
1953 return 0; in mt_adc_l_event()
1962 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_r_event()
1964 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_r_event()
1969 return 0; in mt_adc_r_event()
1978 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_left_event()
1980 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_left_event()
1985 return 0; in mt_pga_left_event()
1994 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_right_event()
1996 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_right_event()
2001 return 0; in mt_pga_right_event()
2019 return 0; in mt_delay_250_event()
2027 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2030 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2033 RG_CLKSQ_EN_SFT, 0,
2038 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2041 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2049 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2059 PDN_DAC_CTL_SFT, 1, NULL, 0),
2062 PDN_ADC_CTL_SFT, 1, NULL, 0),
2065 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2068 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2071 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2074 PDN_RESERVED_SFT, 1, NULL, 0),
2077 0, 0, NULL, 0),
2081 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2082 NULL, 0),
2085 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2087 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2093 0, 0, NULL, 0),
2096 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2098 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2100 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2103 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2106 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2109 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2112 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2118 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2125 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2142 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2148 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2153 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2154 SND_SOC_NOPM, 0, 0,
2159 SND_SOC_NOPM, 0, 0,
2164 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2167 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2173 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2177 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2182 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2183 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2185 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2189 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2194 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2195 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2335 return 0; in mt6358_codec_dai_hw_params()
2377 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2380 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2384 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2388 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2392 0xFFFF, 0x700E); in mt6358_codec_init_reg()
2395 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); in mt6358_codec_init_reg()
2421 return 0; in mt6358_codec_probe()
2445 priv->dmic_one_wire_mode = 0; in mt6358_parse_dt()